ADG467BR Analog Devices Inc, ADG467BR Datasheet - Page 7

• Manufacturer Part Number: ADG467BR
• Description: Analog Switch IC
• Manufacturer: Analog Devices Inc
• Series: ADG467r

Specifications of ADG467BR

• Operating Temperature Range: -40°C To +85°C
• Analog Switch Case Style: SOIC
• No. Of Pins: 8
• Peak Reflow Compatible (260 C): No
• No. Of Circuits: 8
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Voltage - Clamping: ±40V
• Technology: Mixed Technology
• Number Of Circuits: 8
• Applications: General Purpose
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -
• Voltage - Working: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CIRCUIT INFORMATION
Figure 17 below shows a simplified schematic of a channel
protector circuit. The circuit is made up of four MOS transis-
tors—two NMOS and two PMOS. One of the PMOS devices
does not lie directly in the signal path but is used to connect the
source of the second PMOS device to its backgate. This has the
effect of lowering the threshold voltage and so increasing the
input signal range of the channel for normal operation. The
source and backgate of the NMOS devices are connected for the
same reason. During normal operation the channel protectors
have a resistance of 60
low power devices, and even under fault conditions the supply
current is limited to sub microampere levels. All transistors are
dielectrically isolated from each other using a trench isolation
method. This makes it impossible to latch up the channel
protectors. For an explanation, see Trench Isolation section.
Overvoltage Protection
When a fault condition occurs on the input of a channel protec-
tor, the voltage on the input has exceeded some threshold volt-
age set by the supply rail voltages. The threshold voltages are
related to the supply rails as follows. For a positive overvoltage,
the threshold voltage is given by V
threshold voltage of the NMOS transistor (1.5 V typ). In the
REV. A
Figure 17. The Channel Protector Circuit
NMOS
V
DD
typ. The channel protectors are very
OVERVOLTAGE
(SATURATED)
OPERATION
V
SS
Figure 19. Positive Overvoltages Operation of the Channel Protector
V
SS
PMOS
DD
PMOS
– V
(+20V)
V
T
T
N +
V
where V
= 1.5V
NMOS
D
V
SPACE CHARGE
DD
EFFECTIVE
REGION
P –
TN
V
G
N CHANNEL
(V
is the
DD
(V
=15V)
G
– V
N +
V
T
S
= 13.5V)
–7–
case of a negative overvoltage the threshold voltage is given by
V
vice (2 V typ). If the input voltage exceeds these threshold volt-
ages, the output of the channel protector (no load) is clamped at
these threshold voltages. However, the channel protector output
will clamp at a voltage that is inside these thresholds if the out-
put is loaded. For example with an output load of 1 k , V
15 V and a positive overvoltage. The output will clamp at V
V
Figure 19). As can be seen from Figure 19, the current during
fault condition is determined by the load on the output (i.e.,
V
limited to the nano-ampere level.
Figures 18, 20 and 21 show the operating conditions of the
signal path transistors during various fault conditions. Figure 18
shows how the channel protectors operate when a positive over-
voltage is applied to the channel protector.
The first NMOS transistor goes into a saturated mode of opera-
tion as the voltage on its Drain exceeds the Gate voltage (V
the threshold voltage (V
19. The potential at the source of the NMOS device is equal to
V
operations.
N +
Figure 18. Positive Overvoltage on the Channel Protector
(+13.5V)
DD
SS
TN
CLAMP
R voltage drop across the channels of the MOS devices (see
– V
OVERVOLTAGE
– V
– V = 15 V – 1.5 V – 0.6 V = 12.9 V where V is due to I
*V
TN
TP
/R
TN
= NMOS THRESHOLD VOLTAGE (+1.5V)
POSITIVE
PMOS
L
NONSATURATED
where V
. The other MOS devices are in a nonsaturated mode of
). However, if the supplies are off, the fault current is
(+20V)
OPERATION
SATURATED
V
NMOS
TP
V
is the threshold voltage of the PMOS de-
I
NMOS
DD
OUT
(+15V)
TN
). This situation is shown in Figure
SATURATED
R
L
V
NON-
CLAMP
ADG466/ADG467
V
SS
PMOS
V
(–15V)
DD
(+13.5V)
– V
TN
*
V
NMOS
DD
(+15V)
NON-
SATURATED
DD
DD
DD
=
) –
–