ADG412BR Analog Devices Inc, ADG412BR Datasheet - Page 10

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ADG412BR

Manufacturer Part Number
ADG412BR
Description
Multiplexer IC
Manufacturer
Analog Devices Inc
Series
LC²MOSr
Type
Analog Switchr
Datasheet

Specifications of ADG412BR

Peak Reflow Compatible (260 C)
No
Leakage Current
0.1nA
No. Of Circuits
4
Leaded Process Compatible
No
Mounting Type
Surface Mount
No. Of Channels
4
On Resistance Rds(on)
25mohm
Package / Case
16-SOIC
Rohs Status
RoHS non-compliant
Design Resources
Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104)
Function
Switch
Circuit
4 x SPST - NO
On-state Resistance
35 Ohm
Voltage Supply Source
Single, Dual Supply
Voltage - Supply, Single/dual (±)
12V, ±15V
Current - Supply
1µA
Operating Temperature
-40°C ~ 85°C
Package
16SOIC N
Maximum On Resistance
80@10.8V Ohm
Maximum High Level Output Current
30 mA
Maximum Turn-off Time
100(Typ)@±15V ns
Maximum Turn-on Time
175(Typ)@12V ns
Switch Architecture
SPST
Power Supply Type
Single|Dual
Multiplexer Configuration
Quad SPST
Number Of Inputs
4
Number Of Outputs
4
Number Of Channels
4
Analog Switch On Resistance
80@10.8VOhm
Analog Switch Turn On Time
175ns
Analog Switch Turn Off Time
100ns
Package Type
SOIC N
Power Supply Requirement
Single/Dual
Single Supply Voltage (min)
5V
Single Supply Voltage (typ)
12V
Single Supply Voltage (max)
25V
Dual Supply Voltage (min)
±5V
Dual Supply Voltage (typ)
±15V
Dual Supply Voltage (max)
±22V
Power Dissipation
600mW
Supply Current
0.001@±16.5VmA
Mounting
Surface Mount
Pin Count
16
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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ADG411/ADG412/ADG413
APPLICATIONS
Figure 13 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output V
mode, SW1 is opened and the signal is held by the hold
capacitor C
Due to switch and capacitor leakage, the voltage on the hold
capacitor decreases with time. The ADG411/ADG412/ADG413
minimizes this droop due to its low leakage specifications. The
droop rate is further minimized by the use of a polystyrene
hold capacitor. The droop rate for the circuit shown is typically
30 μV/μs.
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches are at the same potential, they have a differential effect
on the op amp AD711, which minimizes charge injection
effects. Pedestal error is also reduced by the compensation
network R
C
H
and C
.
OUT
C
. This compensation network also reduces
follows the input signal V
IN
. In the hold
Rev. D | Page 10 of 16
the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the
pedestal error has a maximum value of 5 mV over the ±10 V
input range. Both the acquisition and settling times are 850 ns.
V
IN
AD845
+15V
–15V
Figure 13. Fast, Accurate Sample-and-Hold
S
S
+15V
SW1
SW2
ADG411
ADG412
ADG413
–15V
+5V
D
D
75 Ω
R
C
2200pF
2200pF
C
1000pF
C
C
H
AD711
+15V
–15V
V
OUT

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