ADF4360-0BCPZRL Analog Devices Inc, ADF4360-0BCPZRL Datasheet - Page 11

• Manufacturer Part Number: ADF4360-0BCPZRL
• Description: IC,FREQUENCY SYNTHESIZER,BICMOS,LLCC,24PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Fanout Distribution, Integer N Synthesizer (RF)r

Specifications of ADF4360-0BCPZRL

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 2.725GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Frequency-max: 2.725GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4360-0EBZ1 - BOARD EVALUATION FOR ADF4360-0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The operating current in the VCO core is programmable in four
steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by
Bits PC1 and PC2 in the control latch.
OUTPUT STAGE
The RF
nected to the collectors of an NPN differential pair driven by
buffered outputs of the VCO, as shown in Figure 15. To allow
the user to optimize the power dissipation vs. the output power
requirements, the tail current of the differential pair is pro-
grammable via Bits PL1 and PL2 in the control latch. Four
current levels may be set: +3.5 mA, +5 mA, +7.5 mA, and
+11 mA. These levels give output power levels of −13 dBm,
−11 dBm, −8.5 dBm, and −6.5 dBm, respectively, using a 50 Ω
resistor to V
both outputs can be combined in a 1 + 1:1 transformer or a 180°
microstrip coupler (see the Output Matching section).
OUT
A and RF
DD
and ac coupling into a 50 Ω load. Alternatively,
OUT
B pins of the ADF4360 family are con-
Rev. A | Page 11 of 24
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to V
Another feature of the ADF4360 family is that the supply current
to the RF output stage is shut down until the part achieves lock as
measured by the digital lock detect circuitry. This is enabled by the
mute-till-lock detect (MTLD) bit in the control latch.
VCO
Figure 15. Output Stage ADF4360-0
DIVIDE BY 2
BUFFER/
DD
RF
.
OUT
A
RF
OUT
ADF4360-0
B