ADF4154BRUZ-RL Analog Devices Inc, ADF4154BRUZ-RL Datasheet - Page 3

• Manufacturer Part Number: ADF4154BRUZ-RL
• Description: IC,FREQUENCY SYNTHESIZER,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4154BRUZ-RL

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 4GHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4154EBZ1 - BOARD EVALUATION FOR ADF4154EB1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPECIFICATIONS
AV
referred to 50 Ω. The operating temperature for the B version is −40°C to +80°C.
Table 1.
Parameter
RF CHARACTERISTICS (3 V)
REFERENCE CHARACTERISTICS
PHASE DETECTOR
CHARGE PUMP
LOGIC INPUTS
LOGIC OUTPUTS
POWER SUPPLIES
NOISE CHARACTERISTICS
1
2
3
4
5
6
Use a square wave for frequencies below f
AC coupling ensures AV
Guaranteed by design. Sample tested to ensure compliance.
This value can be used to calculate phase noise for any application. Use the formula –213 + 10 log(f
seen at the VCO output. The value given is the lowest noise mode.
The phase noise is measured with the EVAL-ADF4154EB1 and the HP8562E spectrum analyzer.
f
REFIN
RF Input Frequency (RF
REF
REF
REF
REF
Phase Detector Frequency
I
I
Matching
I
I
V
V
I
C
V
V
AV
DV
V
I
Low Power Sleep Mode
Phase Noise Figure of Merit
Phase Noise Performance
CP
CP
CP
CP
INH
DD
DD
INH
INL
OH
OL
P
IN
High Value
Low Value
Absolute Accuracy
R
1750 MHz Output
Three-State Leakage Current
= 26 MHz, f
Sink/Source
vs. V
vs. Temperature
, Input Capacitance
DD
/I
DD
, Output Low Voltage
, Input Low Voltage
, Output High Voltage
= DV
IN
IN
IN
IN
SET
, Input High Voltage
INL
, SDV
Input Frequency
Input Sensitivity
Input Capacitance
Input Current
, Input Current
Range
CP
DD
DD
PFD
= SDV
= 26 MHz, offset frequency = 1 kHz, RF
DD
DD
/2 bias. See Figure 14 for a typical circuit.
6
= 2.7 V to 3.3 V; V
1
IN
)
1
5
3
4
MIN
B Version
0.5/4.0
1.0/4.0
10/250
0.7/AV
10
±100
32
5
312.5
2.5
2.7/10
1
2
2
2
1.4
0.6
±1
10
1.4
0.4
2.7/3.3
AV
AV
24
1
−213
−102
.
DD
DD
/5.5
P
DD
= AV
OUT
DD
Unit
GHz min/max
GHz min/max
MHz min/max
V p-p min/max
pF max
μA max
MHz max
mA typ
μA typ
% typ
kΩ min/max
nA typ
% typ
% typ
% typ
V min
V max
μA max
pF max
V min
V max
V min/V max
V min/V max
mA max
μA typ
dBc/Hz typ
dBc/Hz typ
= 1750 MHz, loop B/W = 20 kHz, lowest noise mode.
to 5.5 V; AGND = DGND = 0 V; T
Rev. A | Page 3 of 24
Test Conditions/Comments
See Figure 15 for the input circuit.
−8 dBm/0 dBm min/max. For lower frequencies, ensure slew rate > 400 V/μs.
−10 dBm/0 dBm min/max.
See Figure 14 for input circuit.
For f < 10 MHz, use a dc-coupled, CMOS-compatible square wave,
slew rate > 25 V/μs.
Biased at AV
Programmable. See Table 5.
With R
With R
Sink and source current.
0.5 V < V
0.5 V < V
V
Open-drain 1 kΩ pull-up to 1.8 V.
I
20 mA typical.
@ VCO output.
@ 1 kHz offset, 26 MHz PFD frequency.
OL
CP
= 500 μA.
= V
SET
SET
P
/2.
CP
CP
= 5.1 kΩ.
= 5.1 kΩ.
< V
< V
DD
P
P
/2.
− 0.5 V.
− 0.5 V.
PFD
2
) + 20 log N to calculate the in-band phase noise performance, as
A
= T
MIN
to T
MAX
, unless otherwise noted; dBm
ADF4154