ADAU1445YSVZ-3A Analog Devices Inc, ADAU1445YSVZ-3A Datasheet - Page 57

175MHZ SigmaDSP,2x8 SRCs

ADAU1445YSVZ-3A

Manufacturer Part Number
ADAU1445YSVZ-3A
Description
175MHZ SigmaDSP,2x8 SRCs
Manufacturer
Analog Devices Inc
Series
SigmaDSP®r
Type
Audio Processorr
Datasheet

Specifications of ADAU1445YSVZ-3A

Applications
Automotive Audio
Mounting Type
Surface Mount
Package / Case
100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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The muting is done with a volume ramp and is click and pop free.
If desired, the mute ramp can be disabled for Stereo ASRC[7:4]
(see the Stereo ASRC[7:4] Mute Ramp Disable Register
(Address 0xE143) section).
In the case of the ADAU1446, setting these registers does not
affect system operation in any way.
Stereo ASRC[7:4] Mute Ramp Disable Register
(Address 0xE143)
Table 38. Bit Descriptions of Register 0xE143
Bit
Position
[15:1]
[0]
Description
Reserved
Stereo ASRC[7:4] (Channels[15:8]) mute
ramp disable
0 = enable ramp
1 = disable ramp
Default
0
Rev. A | Page 57 of 92
This single-bit register controls the behavior of Stereo ASRC[7:4]
(Channels[15:8]) on a loss of lock. When Bit 0 is set to the default
(0), Stereo ASRC[7:4] (Channels[15:8]) mute with a volume
ramp. When Bit 0 is set to 1, Stereo ASRC[7:4] mute abruptly.
In addition, setting this bit to 1 ignores the ASRC mute bits
(Bits[3:0]) in Register 0xE141 (see the Stereo ASRC[7:4] Lock
Status and Mute Register (Address 0xE141) section); therefore,
a mute only occurs on a loss of lock.
In the case of the ADAU1446, setting this register does not
affect system operation in any way.
ADAU1445/ADAU1446

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