ADATE302-02BBCZ Analog Devices Inc, ADATE302-02BBCZ Datasheet - Page 40

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ADATE302-02BBCZ

Manufacturer Part Number
ADATE302-02BBCZ
Description
MDual DCL With DAC Levels & PMU
Manufacturer
Analog Devices Inc
Type
DCLr
Datasheet

Specifications of ADATE302-02BBCZ

Applications
Automatic Test Equipment
Mounting Type
Surface Mount
Package / Case
84-CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
ADATE302-02BBCZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADATE302-02
DEFINITION OF SPI WORD
The SPI can take variable length words, depending on the operation. At most, the word is 24 bits longs: 16 bits of data, two channel
selects, one R/W selector, and a 5-bit address.
Depending on the operation, the data can be smaller (or nonexistent in the case of a read operation).
Example 1
Write 16 bits of data to a register or DAC; unused MSBs are ignored. For example, Bit 15 and Bit 14 are ignored, and Bit 13 through Bit 0
are applied to the 14-bit DAC.
Example 2
Write 14 bits of data to the DAC.
Example 3a
Write two bits of data to the 2-bit register.
Example 3b
Write two bits of data to the 2-bit register. Bit 15 through Bit 2 are ignored, while Bit 1 through Bit 0 are applied to the register.
Example 4
Read request and follow with a 2
Table 19. Channel Selection
Channel 1
0
0
1
1
Channel 0
0
1
0
1
Channel Selected
NOP (no channel selected, no register
changes)
Channel 0 selected
Channel 1 selected
Channel 0 and Channel 1 selected
nd
instruction (could be NOP) to clock out the data.
DATA[15:0]
DATA[15:0]
DATA[15:0]
DATA[13:0]
DATA[1:0]
CH[1:0]
Rev. A | Page 40 of 58
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
R/W
CH[1:0]
Table 20. R/W Definition
R/W
0
1
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
ADDR[4:0]
R/W
R/W = 0
R/W
R/W
R/W
Description
Current register specified by address is shifted out
of SDOUT on next shift operation
Current data is written to register specified by
address and channel select
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]

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