ADA4859-3ACPZ-R7 Analog Devices Inc, ADA4859-3ACPZ-R7 Datasheet - Page 14

Sngl Sup HghSpd GN+2 Amp Chrg Pump

ADA4859-3ACPZ-R7

Manufacturer Part Number
ADA4859-3ACPZ-R7
Description
Sngl Sup HghSpd GN+2 Amp Chrg Pump
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADA4859-3ACPZ-R7

Applications
Current Feedback
Number Of Circuits
3
-3db Bandwidth
265MHz
Slew Rate
740 V/µs
Current - Supply
17mA
Current - Output / Channel
19mA
Voltage - Supply, Single/dual (±)
3 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
16-VQFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADA4859-3ACPZ-R7TR
ADA4859-3
VIDEO LINE DRIVER
The ADA4859-3 was designed to excel in video driver applications.
Figure 36 shows a typical schematic for a video driver operating
on bipolar supplies.
In applications that require multiple video loads be driven
simultaneously, the ADA4859-3 can deliver. Figure 37 shows
the ADA4856-3 configured with two video loads, and Figure 38
shows the large signal performance for multiple video loads.
V
IN
+V
10µF
S
CABLE
Figure 38. Large Signal Frequency Response for Various Loads
75Ω
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
+
1µF
1
Figure 37. Video Driver Schematic for Two Video Loads
V
1µF
OUT
0.1µF
75Ω
(R)
1
2
3
4
Figure 36. Video Driver Schematic
V
IN
75Ω
+
CHARGE
(B)
16
PUMP
75Ω
10
+V
5
FREQUENCY (MHz)
15
S
6
10µF
0.1µF
14
7
R
13
L
75Ω
= 75Ω
100
75Ω
8
V
IN
75Ω
75Ω
(R)
V
OUT
12
11
10
9
CABLE
CABLE
R
75Ω
75Ω
L
(B)
PD
= 150Ω
75Ω
75Ω
1000
75Ω
75Ω
V
V
IN
OUT
(G)
V
V
OUT
OUT
Rev. 0 | Page 14 of 16
(G)
1
2
POWER-DOWN
The ADA4859-3 is equipped with a PD (power-down) pin for
all three amplifiers. This allows the user the ability to reduce
the quiescent supply current when an amplifier is not active.
The power-down threshold levels are derived from ground
level. The amplifiers are powered down when the voltage
applied to the PD pin is greater than a certain voltage from
ground. In a 5 V supply application, the voltage is greater than 2 V,
and in a 3.3 V supply application, the voltage is greater than 1.5 V.
The amplifier is enabled whenever the PD pin is left floating
(not connected). If the PD pin is not used, it is best to leave it
floating or connected to ground. Note that the power-down feature
does not control the charge pump output voltage and current.
Table 5. Power-Down Voltage Control
PD Pin
Not Active
Active
LAYOUT CONSIDERATIONS
As is the case with all high speed applications, careful attention
to printed circuit board (PCB) layout details prevents associated
board parasitics from becoming problematic. Proper RF design
technique is mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the board to
provide a low impedance return path. Removing the ground
plane on all layers from the area near the input and output pins
reduces stray capacitance. Locate termination resistors and loads as
close as possible to their respective inputs and outputs. Keep
input and output traces as far apart as possible to minimize
coupling (crosstalk) through the board. Adherence to
microstrip or stripline design techniques for long signal traces
(greater than about 1 inch) is recommended.
POWER SUPPLY BYPASSING
Careful attention must be paid to bypassing the power supply
pins of the ADA4859-3. Use high quality capacitors with low
equivalent series resistance (ESR), such as multilayer ceramic
capacitors (MLCCs), to minimize supply voltage ripple and
power dissipation. A large, usually tantalum, 10 μF to 47 μF
capacitor located in proximity to the ADA4859-3 is required to
provide good decoupling for lower frequency signals. In
addition, locate 0.1 μF MLCC decoupling capacitors as close to
each of the power supply pins as is physically possible, no more
than 1/8-inch away. The ground returns should terminate
immediately into the ground plane. Locating the bypass capacitor
return close to the load return minimizes ground loops and
improves performance.
5 V
<1.5 V
>2 V
3.3 V
<1 V
>1.5 V

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