AD9963BCPZ Analog Devices Inc, AD9963BCPZ Datasheet - Page 39

• Manufacturer Part Number: AD9963BCPZ
• Description: Dual 16B, 200 MSPS D-A Converter
• Manufacturer: Analog Devices Inc

Specifications of AD9963BCPZ

• Package / Case: 72-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Interpolation Filter Coefficients
The interpolation filters, INT0 and INT1, are half-band filters
implemented with a symmetric set of coefficients. Every other
coefficient (even coefficients) except the center coefficient is
zero. The coefficient values for the three interpolation filters are
listed in Table 17 to Table 19.
Table 17. Coefficient Values for INT0
Lower Coefficient
H(1)
H(3)
H(5)
H(7)
H(9)
H(11)
H(13)
H(15)
H(17)
H(19)
H(21)
H(22)
Table 18. Coefficient Values for INT1
Lower Coefficient
H(1)
H(3)
H(5)
H(7)
H(9)
H(10)
Upper Coefficient
H(43)
H(41)
H(39)
H(37)
H(35)
H(33)
H(31)
H(29)
H(27)
H(25)
H(23)
Upper Coefficient
H(19)
H(17)
H(15)
H(13)
H(11)
Value
12
−32
72
−140
252
−422
682
−1086
1778
−3284
10364
16384
Value
26
−138
466
−1314
5058
8191
Rev. 0 | Page 39 of 60
Table 19. Coefficient Values for SRRC Filter
Lower Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(17)
H(18)
H(19)
H(20)
H(21)
H(22)
H(23)
H(24)
H(25)
H(26)
H(27)
Data Flow and Clock Generation
The transmit port TXD[11:0] and TXIQ signals are captured
from by the device with an input latch. The data is then
formatted and buffered in an 8-word deep FIFO. The data exits
the FIFO and is processed by whichever interpolation filters are
enabled. The data is then sampled by the transmit DACs.
The FIFO absorbs any phase drift between the two clock
domains that drive the transmit data. The data is read from the
FIFO by the RDCLK signal. The RDCLK signal is always the
DACCLK divided by the interpolation ratio, I. Data is written to
the FIFO by the WRCLK signal at the quadrature data input
rate, f
and Q samples are interleaved.
Figure 52 shows the block diagram of the transmit path data
flow in full-duplex mode. Also shown in the diagram are the
input data clocking options and the clock doubler selections.
DATA
. f
DATA
is equal to one-half the bus speed because the I
Upper Coefficient
H(53)
H(52)
H(51)
H(50)
H(49)
H(48)
H(47)
H(46)
H(45)
H(44)
H(43)
H(42)
H(41)
H(40)
H(39)
H(38)
H(37)
H(36)
H(35)
H(34)
H(33)
H(32)
H(31)
H(30)
H(29)
H(28)
AD9961/AD9963
Value
−2
−2
8
−4
−21
10
44
−29
−79
66
123
−127
−183
232
251
−394
−326
642
401
−1034
−469
1704
523
−3160
−560
9996
16383