AD9961BCPZRL Analog Devices Inc, AD9961BCPZRL Datasheet - Page 40
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AD9961BCPZRL
Manufacturer Part Number
AD9961BCPZRL
Description
Dual 16B, 200 MSPS D-A Converter
Manufacturer
Analog Devices Inc
Datasheet
1.AD9961BCPZRL.pdf
(60 pages)
Specifications of AD9961BCPZRL
Features
*
Package / Case
72-VFQFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9961/AD9963
The signal on the TXCLK pin can be configured as either an
input or an output. This is configured by the TXCLK_MD
variable (Register 0x31, Bits[5:4]). Whether configured as an
input or an output, the TXCLK signal has the option of being
inverted by configuring the TXCKI_INV or TXCKO_INV
variables.
The transmit path clock doubler is only used when all of the
interpolation filters are bypassed (I = 1) and the transmit path is
configured in bus rate mode (TX_SDR = 1). For more
information about configuring the clock doubler, see Table 22.
TRANSMIT DAC OPERATION
Figure 53 shows a simplified block diagram of one of the transmit
path DACs. Each DAC consists of a current source array, switch
core, digital control logic, and full-scale output current control.
The DAC contains a current source array capable of providing a
nominal full-scale current (I
from the TXIP and TXIN pins are complementary, meaning that
the sum of the two currents always equals the full-scale current of
the DAC. The digital input code to the DAC determines the
effective differential current delivered to the load.
The DACs are powered through the TXVDD pin and can operate
over a 1.8 V to 3.3 V supply range. To facilitate interfacing the
output of the AD9961/AD9963 directly to a range of common-
mode levels, an internal bias voltage is made available through the
TXCML pin.
The DAC full-scale output current is regulated by the reference
control amplifier and is determined by the product of a reference
current, a programmable reference resistor, R
programmable resistor, R
scaling parameters.
TXCLK
TXD[11:0]
Reg 0x31[3]
TXCKI_INV
TXIQ
Reg 0x31[0]
TXCKO_INV
Reg 0x31[6]
TXCLK_MD
0
1
13
SET
, and a pair of programmable gain
EN
OUTFS
1 0
) of 2 mA. The output currents
1 0
LATCH
INPUT
Figure 52. Transmit Path Data Flow and Clock Generation In Full Duplex Mode
EN
Reg 0x31[0]
Reg 0x31[1]
Reg 0x31[2]
TXIQ_HILO
TX_IFIRST
REF
TX_BNRY
TXCLK_MD
Reg 0x31[1]
26
, an internal
FORMAT
FIFO_OFFSET
Reg 0x33[2:0]
Reg 0x34[7:0]
DATA
FIFO_PTR
Rev. 0 | Page 40 of 60
WRCLK
24
POINTER
WRITE
* I DENOTES INTERPOLATION RATIO
AND MONITOR
FIFO RESET
24 BITS
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
REG 6
REG 7
FIFO
Transmit DAC Transfer Function
The output currents from the TXIP and TXIN pins are
complementary, meaning that the sum of the two currents
always equals the full-scale current of the DAC. The digital
input code to the DAC determines the effective differential
current delivered to the load. TXIP provides maximum output
current when all bits are high. The output currents vs. DACCODE
for the DAC outputs are expressed as:
where DACCODE = 0 to 2
There are a number of adjustments that can be made to scale I
to provide programmability in the output signal level.
TXSMPCLK
I
I
REFIO_ADJ[5:0]
TXIP
TXIN
POINTER
READ
IRSET[5:0]
0x6E[5:0]
0x6A[5:0]
12
12
RDCLK
Figure 53. Simplified Block Diagram of I DAC Core
I
REFIO
DACCODE
OUTFS
TX_SDR
Reg 0x31[7]
Q DATA
I DATA
PATH
PATH
0
1
2
N
R
REF
I
TXVDD
TXIP
12
12
I = 1
R
N
0
1
SET
TXDATA
100µA
− 1.
÷ 2
I
OUTFS
DOUBLER
TXDBL_SEL
TX_DBLPW[2:0]
Reg 0x39[0]
Reg 0x3E[5:3]
Q DAC
I DAC
÷ I
DACCLK
IGAIN1[5:0]
0x68[5:0]
IGAIN2
0x69[5:0]
IDAC
DACCLK
TX1P
TX1N
TXCML
OUTFS
(1)
(2)