AD9889ABBCZ-80 Analog Devices Inc, AD9889ABBCZ-80 Datasheet - Page 5

• Manufacturer Part Number: AD9889ABBCZ-80
• Description: IC,TV/VIDEO CIRCUIT,Audio/Video Decoder For MPEG,CMOS,BGA,76PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: HDMI, DVI Transmitterr

Specifications of AD9889ABBCZ-80

• Applications: Recorders, Set-Top Boxes
• Mounting Type: Surface Mount
• Package / Case: 76-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9889B/PCBZ - KIT EVALUATION FOR AD9889B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No.
A1 to A10, B1
to B10, C9,
C10, D9, D10
D1
C2
C1
D2
J3
K3
E2
E1
F2, F1, G2, G1
H2
H1
J7
K1, K2
K10, J10
K7, K8
K4, K5
H10
J2, J5, J8, K9
D5, D6, D7, E7
G4, G5, J1
D4, E4, F4, J4,
G6, J6, K6, F7,
G7, H9, J9
Mnemonic
D[23:0]
CLK
DE
HSYNC
VSYNC
EXT_SW
HPD
S/PDIF
MCLK
I
SCLK
LRCLK
PD/A0
TxC−/TxC+
Tx2−/Tx2+
Tx1−/Tx1+
Tx0−/Tx0+
INT
AVDD
DVDD
PVDD
GND
2
S[3:0]
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
P
P
P
P
1
Description
Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from 1.8 V to 3.3 V.
Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V.
Horizontal SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Vertical SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this pin and ground.
Hot Plug Detect Signal. This indicates to the interface whether the receiver is connected. 1.8 V to
5.0 V CMOS logic level.
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a Sony/Philips
digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Reference Clock. 128 × N × f
256 × f
I
through I
I
Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.
Power-Down Control and I
PD/A0 pin state when the supplies are applied to the AD9889A. 1.8 V to 3.3 V CMOS logic level.
Differential Clock Output. Differential clock output at pixel clock rate; transition minimized
differential signaling (TMDS) logic level.
Differential Output Channel 2. Differential output of the red data at 10× the pixel clock rate; TMDS
logic level.
Differential Output Channel 1. Differential output of the green data at 10× the pixel clock rate;
TMDS logic level.
Differential Output Channel 0. Differential output of the blue data at 10× the pixel clock rate; TMDS
logic level.
Interrupt. CMOS logic level. A 2 kΩ pull up resistor to interrupt the microcontroller IO supply is
recommended.
1.8 V Power Supply for TMDS Outputs.
1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to the digital logic
and I/Os. They should be filtered and as quiet as possible.
1.8 V PLL Power Supply. The most sensitive portion of the AD9889A is the clock generation
circuitry. These pins provide power to the clock PLL. The designer should provide quiet, noise-free
power to these pins.
Ground. The ground return for all circuitry on-chip. It is recommended that the AD9889A be
assembled on a single, solid ground plane with careful attention given to ground current paths.
2
2
S Audio Data Inputs. These represent the eight channels of audio (two per input) available
S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
S
, 384 × f
2
Figure 2. 76-Ball BGA Configuration (Top View)
S. Supports CMOS logic levels from 1.8 V to 3.3 V.
S
, or 512 × f
10
9
Rev. 0 | Page 5 of 12
BOTTOM VIEW
8 7 6
(Not to Scale)
2
S
C Address Selection. The I
. 1.8 V to 3.3 V CMOS logic level.
5 4
3 2 1
S
with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (f
A
B
C
D
E
F
G
H
J
K
2
C address and the PD polarity are set by the
AD9889A
S
),