AD9863BCPZ-50 Analog Devices Inc, AD9863BCPZ-50 Datasheet - Page 30

• Manufacturer Part Number: AD9863BCPZ-50
• Description: IC,RF Modulator/Demodulator,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9863BCPZ-50

• Rf Type: WLL, WLAN
• Features: 12-bit ADC(s), 12-bit DAC(s)
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9863
Table 17. Register Bit Descriptions
Register Bit
Register 0x00: General
Register 0x01: Clock Mode
Register 0x02: Power-Down
Register 0x03/04: Rx Power-Down
Register 0x05: Rx Power-Down
Bit 7: SDIO BiDir (Bidirectional)
Bit 6: LSB First
Bit 5: Soft Reset
Bit 7 to Bit 5: Clk_Mode
Bit 2: Enable IFACE2 clkout
Bit 1: Inv clkout (IFACE3)
Bit 7 to Bit 5: Tx Analog
Bit 4: Tx Digital (Power-Down)
Bit 3: Rx Digital (Power-Down)
Bit 2: PLL Power-Down
Bit 1: PLL Output Disconnect
Bit 7: Rx_A Analog/
Bit 6: Rx_A DC Bias/
Bit 7: Rx Analog Bias (Power-
(Power-Down)
Rx_B Analog (Power-Down)
Rx_B DC Bias (Power-Down)
Down)
Description
Default setting is low, which indicates that the SPI serial port uses dedicated input and output lines
(4-wire interface), SDIO pins and SDO pins, respectively. Setting this bit high configures the serial
port to use the SDIO pin as a bidirectional data pin.
Default setting is low, which indicates MSB first SPI port access mode. Setting this bit high
configures the SPI port access to LSB first mode.
Writing a high to this register resets all the registers to their default values and forces the PLL to
relock to the input clock. The soft reset bit is a one-shot register and is cleared immediately after
the register write is completed.
These bits represent the clocking interface for the various modes. Setting 000 is default. Setting 111
is used for clone mode. Refer to the Summary of Flexible I/O Modes section for a definition of clone
mode.
Enables the IFACE2 port to be an output clock. Also inverts the IFACE2 output clock in full-duplex mode.
Inverts the output clock on IFACE3.
Three options are available to reduce analog power consumption for the Tx channels. The first two
options disable the analog output from Tx Channel A or B independently, and the third option
disables the output of both channels and reduces the power consumption of some of the addi-
tional analog support circuitry for maximum power savings. With all three options, the DAC bias
current is not powered down, so recovery times are fast (typically a few clock cycles). The list below
explains the different modes and settings used to configure them.
Default is low, which enables the digital section of the transmit path to operate as programmed
through other registers. By setting this bit high, the digital blocks are not clocked to reduce power
consumption. When enabled, the Tx outputs are static, holding their last update values.
Setting this bit high powers down the digital section of the receive path of the chip. Typically, any
unused digital blocks are automatically powered down.
Setting this register bit high forces the CLKIN2 PLL multiplier to a power-down state. This mode can
be used to conserve power or to bypass the internal PLL. To operate the AD9863 when the PLL is
bypassed, CLKIN2 must be supplied with a clock equal to the fastest Tx path clock.
Setting this register bit high disconnects the PLL output from the clock path. If the PLL is enabled, it
locks or stays locked as normal.
Either ADC or both ADCs can be powered down by setting the appropriate register bit high. The
entire analog circuitry of the Rx channel is powered down, including the differential references,
input buffer, and the internal digital block. The band gap reference remains active for quick
recovery.
Setting either of these bits high powers down the input common-mode bias network for the
respective channel and requires an input signal to be properly dc-biased. By default, these bits are
low, and the Rx inputs are self-biased to approximately AVDD/2 and accept an ac-coupled input.
Setting this bit high powers down all analog bias circuits related to the receive path (including the
differential reference buffer). Because bias circuits are powered down, there is an additional power
saving, but also a longer recovery time relative to other Rx power-down options.
Setting
000
001
010
011
100
101
110
111
Power-down Tx B channel analog output [0 1 0]
Power-down Tx A and Tx B analog outputs [1 1 1]
Power-down option bits setting [7:5]
Power-down Tx A channel analog output [1 0 0]
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Mode
Standard FD, HD12, HD24 Clock (Modes 1, 4, 7)
Optional FD timing (Mode 2)
Not used
Optional HD24 timing (Mode 5)
Not used
Optional HD12 timing (Mode 8)
Not used
Clone Mode (Mode 10)