AD9859/PCBZ Analog Devices Inc, AD9859/PCBZ Datasheet - Page 18

• Manufacturer Part Number: AD9859/PCBZ
• Description: 400 MSPS DDS W/ 10 BIT DAC EvalBd
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9859/PCBZ

• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Embedded: No
• Utilized Ic / Part: AD9859
• Primary Attributes: 10-Bit DAC, 32-Bit Tuning Word Width
• Secondary Attributes: 400MHz, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9859
External Shaped On-Off Keying Mode Operation
The external shaped on-off keying mode is enabled by writing
CFR1<25> to a Logic 1 and writing CFR1<24> to a Logic 0.
When configured for external shaped on-off keying, the
content of the ASFR becomes the scale factor for the data path.
The scale factors are synchronized to SYNC_CLK via the
I/O UPDATE functionality.
Synchronization; Register Updates (I/O UPDATE)
Functionality of the SYNC_CLK and I/O UPDATE
Data into the AD9859 is synchronous to the SYNC_CLK signal
(supplied externally to the user on the SYNC_CLK pin). The
I/O UPDATE pin is sampled on the rising edge of the
SYNC_CLK.
Internally, SYSCLK is fed to a divide-by-4 frequency divider to
produce the SYNC_CLK signal. The SYNC_CLK signal is pro-
vided to the user on the SYNC_CLK pin. This enables synchro-
nization of external hardware with the device’s internal clocks.
This is accomplished by forcing any external hardware to obtain
its timing from SYNC_CLK. The I/O UPDATE signal coupled
with SYNC_CLK is used to transfer internal buffer contents
TO CORE LOGIC
SYSCLK
Figure 19. I/O Synchronization Block Diagram
Q
D
REGISTER
MEMORY
OSK
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DETECTION
SYNC_CLK
GATING
÷ 4
LOGIC
EDGE
Q
I/O BUFFER
D
LATCHES
PROFILE<1:0>
into the control registers of the device. The combination of the
SYNC_CLK and I/O UPDATE pins provides the user with
constant latency relative to SYSCLK, and also ensures phase
continuity of the analog output signal when a new tuning word
or phase offset value is asserted. Figure 19 demonstrates an I/O
UPDATE timing cycle and synchronization.
Notes on synchronization logic:
•
•
The I/O UPDATE signal is edge detected to generate a
single rising edge clock signal that drives the register bank
flops. The I/O UPDATE signal has no constraints on duty
cycle. The minimum low time on I/O UPDATE is one
SYNC_CLK clock cycle.
The I/O UPDATE pin is set up and held around the rising
edge of SYNC_CLK and has zero hold time and 4 ns setup
time.
Q
D
0
SYNC_CLK
DISABLE
I/O UPDATE
SCLK
SDI
CS