AD9834BRUZ-REEL Analog Devices Inc, AD9834BRUZ-REEL Datasheet - Page 6

• Manufacturer Part Number: AD9834BRUZ-REEL
• Description: IC,Numeric-Controlled Oscillator,1-CHANNEL,CMOS,TSSOP,20PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9834BRUZ-REEL

• Design Resources: Amplitude Control Circuit for AD9834 Waveform Generator (CN0156)
• Resolution (bits): 10 b
• Master Fclk: 50MHz
• Tuning Word Width (bits): 28 b
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD9834EBZ - BOARD EVAL FOR AD9834
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9834
TIMING CHARACTERISTICS
DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
Timing Diagrams
1
2
3
4
5
6
7
8 MIN
8 MAX
9
10
11
11A
12
Guaranteed by design, not production tested.
1
SDATA
FSYNC
SCLK
Limit at T
20/13.33
8/6
8/6
25
10
10
5
10
t
5
3
8
8
5
4
− 5
t
12
MIN
FSELECT,
PSELECT
to T
MCLK
t
MAX
7
D15
VALID DATA
D14
t
6
ns min
ns min
ns min
Unit
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns min
t
5
MCLK
t
11
Figure 4. Control Timing
Figure 5. Serial Timing
Figure 3. Master Clock
Rev. C | Page 6 of 36
VALID DATA
Test Conditions/Comments
MCLK period: 50 MHz/75 MHz
MCLK high duration: 50 MHz/75 MHz
MCLK low duration: 50 MHz/75 MHz
SCLK period
SCLK high duration
SCLK low duration
FSYNC-to-SCLK falling edge setup time
FSYNC-to-SCLK hold time
Data setup time
Data hold time
FSELECT, PSELECT setup time before MCLK rising edge
FSELECT, PSELECT setup time after MCLK rising edge
SCLK high to FSYNC falling edge setup time
D2
t
2
t
t
4
1
t
t
3
9
D1
t
10
t
11A
VALID DATA
D0
t
8
D15
D14