AD9833BRM-REEL7 Analog Devices Inc, AD9833BRM-REEL7 Datasheet - Page 13

• Manufacturer Part Number: AD9833BRM-REEL7
• Description: IC,Numeric-Controlled Oscillator,25MHZ,CMOS,TSSOP,10PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9833BRM-REEL7

• Rohs Status: RoHS non-compliant
• Resolution (bits): 10 b
• Master Fclk: 25MHz
• Tuning Word Width (bits): 28 b
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• For Use With: EVAL-AD9833EBZ - BOARD EVAL FOR AD9833
• Lead Free Status / Rohs Status: Not Compliant

FUNCTIONAL DESCRIPTION
SERIAL INTERFACE
The AD9833 has a standard 3-wire serial interface that is
compatible with SPI®, QSPI™, MICROWIRE™, and DSP
interface standards.
Data is loaded into the device as a 16-bit word under the
control of a serial clock input, SCLK. The timing diagram for
this operation is given in Figure 4.
The FSYNC input is a level-triggered input that acts as a frame
synchronization and chip enable. Data can be transferred into the
device only when FSYNC is low. To start the serial data transfer,
FSYNC should be taken low, observing the minimum FSYNC-
to-SCLK falling edge setup time, t
data is shifted into the input shift register of the device on the
falling edges of SCLK for 16 clock pulses. FSYNC may be taken
high after the 16th falling edge of SCLK, observing the minimum
SCLK falling edge to FSYNC rising edge time, t
FSYNC can be kept low for a multiple of 16 SCLK pulses and
then brought high at the end of the data transfer. In this way, a
continuous stream of 16-bit words can be loaded while FSYNC
is held low, FSYNC only going high after the 16th SCLK falling
edge of the last word loaded.
SCLK can be continuous, or alternatively, it can idle high or low
between write operations, but it must be high when FSYNC
goes low (t
For an example of programming the AD9833, see the AN-1070
Application Note, Programming the AD9833/AD9834, at
www.analog.com.
POWERING UP THE AD9833
The flowchart in Figure 26. shows the operating routine for the
AD9833. When the AD9833 is powered up, the part should be
reset. This will reset appropriate internal registers to zero to
11
).
SLEEP12
SLEEP1
RESET
MODE + OPBITEN
DIV2
OPBITEN
DB15
0
DB14
0
ACCUMULATOR
7
. After FSYNC goes low, serial
DB13
(28-BIT)
PHASE
B28
DB12
HLB
FSELECT
DB11
8
. Alternatively,
ROM
PSELECT
SIN
DB10
Figure 24. Function of Control Bits
DB9
0
Rev. C | Page 13 of 24
MUX
0
1
RESET
DB8
SLEEP1
DIVIDE
DB7
BY 2
provide an analog output of midscale. To avoid spurious DAC
outputs while the AD9833 is being initialized, the reset bit
should be set to 1 until the part is ready to begin generating an
output. RESET does not reset the phase, frequency, or control
registers. These registers will contain invalid data, and therefore,
should be set to a known value by the user. The reset bit should
then be set to 0 to begin generating an output. The data will appear
on the DAC output eight MCLK cycles after reset is set to 0.
LATENCY
Associated with each asynchronous write operation in the AD9833
is a latency. If a selected frequency/phase register is loaded with
a new word, there is a delay of seven to eight MCLK cycles before
the analog output will change. (There is an uncertainty of one
MCLK cycle, because it depends on the position of the MCLK
rising edge when the data is loaded into the destination register.)
CONTROL REGISTER
The AD9833 contains a 16-bit control register that sets up the
AD9833 as the user wants to operate it. All control bits, except
mode, are sampled on the internal negative edge of MCLK.
Table 6 describes the individual bits of the control register. The
different functions and the various output options from the AD9833
are described in more detail in the Frequency and Phase
Registers section.
To inform the AD9833 that the contents of the control register
will be altered, D15 and D14 must be set to 0 as shown in Table 5.
Table 5. Control Register
D15
0
SLEEP12
DB6
1
MUX
0
D14
0
(LOW POWER)
10-BIT DAC
OPBITEN
DB5
(ENABLE)
DIGITAL
OUTPUT
D13
DB4
AD9833
0
DIV2
DB3
DB2
0
MODE
DB1
Control Bits
VOUT
DB0
0
AD9833
D0