AD977AR-REEL Analog Devices Inc, AD977AR-REEL Datasheet - Page 10

• Manufacturer Part Number: AD977AR-REEL
• Description: IC,A/D CONVERTER,SINGLE,16-BIT,BICMOS,SOP,20PIN
• Manufacturer: Analog Devices Inc

Specifications of AD977AR-REEL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 100mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• For Use With: EVAL-AD977CB - BOARD EVAL FOR AD977EVAL-AD977ACB - BOARD EVAL FOR AD977A

AD977/AD977A
EXTERNAL DISCONTINUOUS CLOCK DATA READ
DURING CONVERSION NO SYNC OUTPUT
GENERATED
Figure 5 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a discon-
tinuous external clock, without the generation of a SYNC out-
put. After a conversion is initiated, indicated by BUSY going
low, the result of the previous conversion can be read while CS
is low and R/C is high. In this mode CS can be tied low. The
MSB will be valid on the 1st falling edge and the 2nd rising
edge of DATACLK. The LSB will be valid on the 16th falling
edge and the 17th rising edge of DATACLK. A minimum of 16
clock pulses are required for DATACLK if the receiving device
will be latching data on the falling edge of DATACLK. A mini-
mum of 17 clock pulses are required for DATACLK if the
receiving device will be latching data on the rising edge of
DATACLK. Approximately 40 ns after the 17th rising edge of
DATACLK (if provided) the DATA output pin will reflect the
state of the TAG input pin during the first rising edge of
DATACLK.
For both the AD977 and the AD977A the data should be
clocked out during the first half of BUSY so not to degrade
conversion performance. For the AD977 this requires use of a
4.8 MHz DATACLK or greater with data being read out as
soon as the conversion process begins. For the AD977A it
requires use of a 10 MHz DATACLK or greater.
It is not recommended that data be shifted through the TAG
input in this mode as it will certainly result in clocking of data
during the second half of the conversion.
DATACLK
BUSY
SYNC
DATA
EXT
R/C
t
2
t
1
INT
t
21
t
15
t
18
0
t
13
t
12
t
BIT 15
(MSB)
14
1
CS
BIT 14
t
20
EXTERNAL DISCONTINUOUS CLOCK DATA READ
AFTER CONVERSION WITH SYNC OUTPUT GENERATED
Figure 6 illustrates the method by which data from conversion
“n” can be read after the conversion is complete using a discon-
tinuous external clock, with the generation of a SYNC output.
What permits the generation of a SYNC output is a transition of
DATACLK while either CS is high or while both CS and R/C
are low. After a conversion is complete, indicated by BUSY
returning high, the result of that conversion can be read while
CS is Low and R/C is high. In this mode CS can be tied low. In
Figure 6 clock pulse #0 is used to enable the generation of a
SYNC pulse. The SYNC pulse is actually clocked out approxi-
mately 40 ns after the rising edge of clock pulse #1. The SYNC
pulse will be valid on the falling edge of clock pulse #1 and the
rising edge of clock pulse #2. The MSB will be valid on the
falling edge of clock pulse #2 and the rising edge of clock pulse
#3. The LSB will be valid on the falling edge of clock pulse #17
and the rising edge of clock pulse #18. Approximately 40 ns
after the rising edge of clock pulse #18 the DATA output pin
will reflect the state of the TAG input pin during the rising edge
of clock pulse #2. The advantage of this method of reading data
is that it is not being clocked out during a conversion and there-
fore conversion performance is not degraded.
When reading data after the conversion is complete, with the
highest frequency permitted for DATACLK (15.15 MHz),
and with the AD977A, the maximum possible throughput is
approximately 195 kHz and not the rated 200 kHz.
For details on use of the TAG input with this mode see the Use
of the TAG Input section.
2
t
15
18
(LSB)
BIT 0
16
t
22