AD9773BSVZRL Analog Devices Inc, AD9773BSVZRL Datasheet - Page 31

• Manufacturer Part Number: AD9773BSVZRL
• Description: 12Bit 160 MSPS Dual TxDAC+ DAC
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9773BSVZRL

• Settling Time: 11ns
• Number Of Bits: 12
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 410mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DATACLK INVERSION
(Control Register 02h, Bit 4)
By programming this bit, the DATACLK signal shown in
Figure 52 can be inverted. With inversion enabled, t
the time between the rising edge of CLKIN and the falling edge
of DATACLK. No other effect on timing occurs.
DATA AT PORTS
DATACLK DRIVER STRENGTH
(Control Register 02h, Bit 5)
The DATACLK output driver strength is capable of driving
>10 mA into a 330 Ω load while providing a rise time of 3 ns.
Figure 53 shows DATACLK driving a 330 Ω resistive load at a
frequency of 50 MHz. By enabling the drive strength option
(Control Register 02h, Bit 5), the amplitude of DATACLK under
these conditions increases by approximately 200 mV.
–0.5
3.0
2.5
2.0
1.5
1.0
0.5
1 AND 2
0
0
Figure 53. DATACLK Driver Capability into 330 Ω at 50 MHz
DATACLK
Figure 52. Timing Requirements in Two-Port
CLKIN
10
Input Mode with PLL Enabled
t
S
t
H
20
t
OD
TIME (ns)
DELTA APPROX. 2.8ns
30
t
t
S
H
= 0.0ns (MAX)
= 2.5ns (MAX)
40
OD
refers to
50
Rev. D | Page 31 of 60
PLL ENABLED, ONE-PORT MODE
(Control Register 02h, Bits [6:1] and 04h, Bits [7:1]
In one-port mode, the I and Q channels receive their data from
an interleaved stream at Digital Input Port 1. The function of
Pin 32 is defined as an output (ONEPORTCLK) that generates a
clock at the interleaved data rate, which is 2× the internal input
data rate of the I and Q channels. The frequency of CLKIN is
equal to the internal input data rate of the I and Q channels.
The selection of the data for the I or Q channel is determined by
the state of the logic level at Pin 31 (IQSEL when the AD9773 is
in one-port mode) on the rising edge of ONEPORTCLK. Under
these conditions, IQSEL = 0 latches the data into the I channel
on the clock rising edge, while IQSEL = 1 latches the data into
the Q channel. It is possible to invert the I and Q selection by
setting Control Register 02h, Bit 1 to the invert state (Logic 1).
Figure 54 illustrates the timing requirements for the data inputs
as well as the IQSEL input. Note that the 1× interpolation rate is
not available in the one-port mode.
The DAC output sample rate in one port mode is equal to
CLKIN multiplied by the interpolation rate. If zero stuffing is
used, another factor of 2 must be included to calculate the DAC
sample rate.
ONEPORTCLK INVERSION
(Control Register 02h, Bit 2)
By programming this bit, the ONEPORTCLK signal shown in
Figure 54 can be inverted. With inversion enabled, t
the delay between the rising edge of the external clock and the
falling edge of ONEPORTCLK. The setup and hold times, t
and t
There is no other effect on timing.
H
, are with respect to the falling edge of ONEPORTCLK.
OD
AD9773
refers to
S