AD9742ACP-PCBZ Analog Devices Inc, AD9742ACP-PCBZ Datasheet - Page 15

• Manufacturer Part Number: AD9742ACP-PCBZ
• Description: Eval Board 12-BIT 210 MSPS TxDAC DAC IC
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9742ACP-PCBZ

• Number Of Dac's: 1
• Number Of Bits: 12
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 210M
• Data Interface: Parallel
• Settling Time: 11ns
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9742
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 26. These termination resistors are untrimmed and can
vary up to ±20%. However, matching between the resistors
should generally be better than ±1%.
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relation-
ship between the position of the clock edges and the time at
which the input data changes. The AD9742 is rising edge
triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the goal
when applying the AD9742 is to make the data transition close
to the falling clock edge. This becomes more important as the
sample rate increases. Figure 27 shows the relationship of SFDR
to clock placement with different sample rates. Note that at the
lower sample rates, more tolerance is allowed in clock place-
ment, while at higher rates, more care must be taken.
Sleep Mode Operation
The AD9742 has a power-down function that turns off the
output current and reduces the supply current to less than 6 mA
over the specified supply range of 2.7 V to 3.6 V and tempera-
ture range. This mode can be activated by applying a Logic
Level 1 to the SLEEP pin. The SLEEP pin logic threshold is
equal to 0.5 Ω AVDD. This digital input also contains an
Figure 27. SFDR vs. Clock Placement @ f
CLK+
CLK–
75
70
65
60
55
50
45
40
35
–3
50MHz SFDR
50Ω
Figure 26. Clock Termination in PECL Mode
–2
V
TT
= 1.3V NOM
20MHz SFDR
50Ω
–1
CLOCK
RECEIVER
AD9742
ns
0
OUT
50MHz SFDR
= 20 MHz and 50 MHz
1
TO DAC CORE
2
3
Rev. B | Page 15 of 32
active pull-down circuit that ensures that the AD9742 remains
enabled if this input is left disconnected. The AD9742 takes less
than 50 ns to power down and approximately 5 µs to power
back up.
POWER DISSIPATION
The power dissipation, P
several factors that include:
•
•
•
•
The power dissipation is directly proportional to the analog
supply current, I
is directly proportional to I
insensitive to f
digital input waveform, f
29 shows I
(f
OUT
/f
The power supply voltages (AVDD, CLKVDD, and DVDD)
The full-scale current output I
The update rate f
The reconstructed digital input waveform
CLOCK
20
18
16
14
12
10
35
30
25
20
15
10
0.01
8
6
4
2
0
0
2
DVDD
) for various update rates with DVDD = 3.3 V.
4
CLOCK
as a function of full-scale sine wave output ratios
Figure 29. I
AVDD
. Conversely, I
6
, and the digital supply current, I
CLOCK
Figure 28. I
CLOCK
DVDD
D
8
RATIO (f
, of the AD9742 is dependent on
OUTFS
vs. Ratio @ DVDD = 3.3 V
I
210MSPS
165MSPS
125MSPS
, and digital supply DVDD. Figure
OUTFS
65MSPS
10
, as shown in Figure 28, and is
AVDD
0.1
OUT
DVDD
(mA)
/f
OUTFS
vs. I
12
CLOCK
is dependent on both the
OUTFS
14
)
16
18
AD9742
DVDD
20
1
. I
AVDD