AD9739BBC Analog Devices Inc, AD9739BBC Datasheet - Page 47
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AD9739BBC
Manufacturer Part Number
AD9739BBC
Description
14 Bit 2.5 GSPS DAC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9739BBCZ.pdf
(56 pages)
Specifications of AD9739BBC
Number Of Bits
14
Data Interface
Serial
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
980mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
160-CSPBGA
Number Of Channels
1
Resolution
14b
Interface Type
LVDS
Single Supply Voltage (typ)
3.3V
Dual Supply Voltage (typ)
Not RequiredV
Power Supply Requirement
Analog and Digital
Output Type
Current
Integral Nonlinearity Error
±1.3LSB
Single Supply Voltage (min)
3.1V
Single Supply Voltage (max)
3.5V
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
160
Package Type
CSP-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Settling Time
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9739BBCZ
Manufacturer:
EXAR
Quantity:
101
Company:
Part Number:
AD9739BBCZ
Manufacturer:
Analog Devices Inc
Quantity:
135
Part Number:
AD9739BBCZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
OPTIMIZING THE CLOCK COMMON-MODE
VOLTAGE
To optimize the interface and handoff timing, there is an
additional system that sets the common-mode voltage of the
clock, which can be used to properly align the crossing point of
the DACCLK_P and DACCLK_N signals to ensure that the
duty cycle of the clock is set properly. Figure 99 shows how the
common-mode voltage of DACCLK_P and DACCLK_N is set.
Eight switches controlled by the SPI bits, CLKP_OFFSET[3:0]
(Register 0x22, Bits[3:0]) and CLKN_OFFSET[3:0] (Register
0x23, Bits[3:0]), for both the DACCLK_P and DACCLK_N
signals.
The DIR_P (Register 0x22, Bit 4) and DIR_N (Register 0x23,
Bit 4) bits determine the direction of the adjustment. If
DIR_P/DIR_N is low, the common-mode voltage decreases
with the CLKP_OFFSET/CLKN_OFFSET values. If DIR_P/
DIR_N is high, the common-mode voltage increases with the
CLKP_OFFSET/CLKN_OFFSET values, as shown in Figure 100.
When both CLKP_OFFSET and CLKN_OFFSET bits are set to
zero, the feedback path forces the common-mode voltage to be
set to approximately 0.9 V. The optimal ac performance occurs
at a setting of −15 on both the CLKP and CLKN offset bits.
MaxSkew + Jitter = 800 ps – 344 ps – 100 ps
MaxSkew + Jitter = 456 ps
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
–15 –13 –11 –9 –7 –5 –3 –1
CLKx_OFFSET
CLKx_OFFSET
DACCLK_x
Figure 100. Common-Mode Voltage with Respect to
DIR_x = 0
DIR_x = 1
CLKP_OFFSET/CLKN_OFFSET and DIR_P/DIR_N
Figure 99. Clock Common-Mode Control
CLKVDD
OFFSET CODE
1
3
5
7
9 11 13 15
CLKP
CLKN
Rev. 0 | Page 47 of 56
ANALOG CONTROL REGISTERS
The AD9739 includes some registers for optimizing its analog
performance. These registers include noise reduction in the
output current mirror and output current mirror headroom
adjustments.
MIRROR ROLL-OFF FREQUENCY CONTROL
Using MSEL[1:0] (Register 0x33, Bits[1:0]), the user can adjust
the noise contribution of the internal current mirror to
optimize the 1/f noise. Figure 101 shows the MSEL bits vs. the
1/f noise with 20 mA full-scale current into a 50 Ω resistor.
VOLTAGE REFERENCE
The AD9739 output current is set by a combination of
digital control bits and the I120 reference current, as shown
in Figure 102.
The reference current is obtained by forcing the band gap
voltage across an external 10 kΩ resistor from I120 (Pin B14) to
ground. The 1.2 V nominal band gap voltage (VREF) generates
a 120 μA reference current in the 10 kΩ resistor. This current is
adjusted digitally by FSC[9:0] (Register 0x06 and Register 0x07)
to set the output full-scale current I
The full-scale output current range is approximately 8 mA to
31 mA for register values from 0x000 to 0x3FF. The default
value of 0x200 generates 20 mA full scale. The typical range is
shown in Figure 103.
IOUTFS = 0.0226 × FSC[9:0] + 8.5845
–120
–125
–130
–135
–140
–110
–115
1nF
1
AVSS
Figure 101. 1/f Noise with Respect to the MSEL Bits
10kΩ
VREF
I120
Figure 102. Voltage Reference Circuit
I120
V
1.2V
BG
AD9739
–
+
FREQUENCY (kHz)
10
CURRENT
SCALING
FSC[9:0]
FS
.
IFULL-SCALE
DAC
AD9739
100