AD9739-CMTS-EBZ Analog Devices Inc, AD9739-CMTS-EBZ Datasheet - Page 51

• Manufacturer Part Number: AD9739-CMTS-EBZ
• Description: 14 Bit 2.5 GSPS DAC
• Manufacturer: Analog Devices Inc

Specifications of AD9739-CMTS-EBZ

• Number Of Dac's: 1
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 2.5G
• Data Interface: SPI™
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9739
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 40.
Register
PHS_DET
MU_DUTY
MU_CNT1
MU_CNT2
MU_CNT3
MU_CNT4
1
Table 41.
Register
MU_STAT1
1
5.
Table 42. Master Mode
Register
LVDS_REC_
CNT1
LVDS_REC_
CNT6
1
Table 43. Slave Mode
Register
LVDS_REC_
CNT1
LVDS_REC_
CNT6
1
The two-digit number is the decimal representation of the address.
The two-digit number is the decimal representation of the address.
The two-digit number is the decimal representation of the address.
The two-digit number is the decimal representation of the address.
The status readback bits for the mu controller, if the controller is locked, are as shown in Table 41.
To read back the present mu delay and phase values, it is necessary to set the read bit high and then low before the values can be read
back.
•
•
•
There is a lower speed limit on the DAC clock. The mu controller was not designed to run at DAC clock speeds of 1 GHz and below.
For applications in these frequency ranges, it is recommended that the mu controller be disabled completely.
If synchronizing multiple parts, enable the synchronization controller and ensure that it locks. If synchronization is not necessary,
skip Step 5 and go to Step 6.
Read—Register 0x26, Bit 3 (set high to read). For subsequent reads, this bit must be brought low, then high again. It cannot be
left high to continuously read the MUDEL value.
Mu delay readback—Register 0x28, Bits[7:0] and Register 0x27, Bit 7 (a total of nine bits in the readback; the maximum mu
delay value is d432 or x1B0). This now represents the value the controller locked to, not the starting value of the search.
MUD_PH_Readback, Register 0x27, Bits[4:0]—This represents the phase the controller is locked to.
Address
0x24
0x25
0x26
0x27
0x28
0x29
Address
0x10
0x15
Address
0x10
0x15
Address
0x2A
36
37
38
39
40
41
16
21
16
21
1
1
1
42
1
N/A
Bit 7
N/A
MU_DUTY
AUTO_EN
(1)
MUDEL[0]
(0)
MUDEL[8]
(0)
Search_Tol
(1)
Bit 7
SYNC_
FLG_RST
(0)
SYNC_
GAIN[1](0)
Bit 7
SYNC_
FLG_RST
(0)
SYNC_
GAIN[1]
(0)
Bit 7
N/A
Bit 6
SYNC_
LOOP_ON
(1)
SYNC_
GAIN[0](1)
Bit 6
SYNC_
LOOP_ON
(1)
SYNC_
GAIN[0](1)
Bit 6
N/A
POS/NEG (0)
Slope (0)
SrchMode[1]
(1)
MUDEL[7]
(1)
Retry (1)
Bit 6
N/A
Bit 5
N/A
Bit 5
SYNC_
MST/SLV
(1)
SYNCOUT_
PH[1](0)
Bit 5
SYNC_
MST/SLV
(0)
SYNCOUT_
PH[1](0)
Bit 5
PHS_DET
AUTO_EN (1)
ADJ[5](0)
Mode[1] (0)
SrchMode
[0] (0)
MUDEL[6] (1)
ContRst (0)
Bit 4
N/A
Rev. 0 | Page 51 of 56
Bit 4
SYNC_
CNT_ENA
(1)
SYNCOUT_
PH[0](0)
Bit 4
SYNC_
CNT_ENA
(1)
SYNCOUT_
PH[0](0)
Bit 4
CMP_BST
(1)
ADJ[4] (0)
Mode[0]
(0)
SetPhs[4]
(0)
MUDEL[5]
(0)
Guard[4]
(0)
Bit 3
N/A
Bit 3
N/A
LCKTHR[3]
(0)
Bit 3
N/A
LCKTHR[3]
(0)
Bit 3
Bias[3]
(0)
ADJ[3]
(0)
Read (0)
SetPhs
[3] (0)
MUDEL
[4] (1)
Guard[3]
(1)
Bit 2
N/A
Bit 2
RCVR_
FLG_RST
(0)
LCKTHR[2]
(0)
Bit 2
RCVR_
FLG_RST
(0)
LCKTHR[2]
(0)
Bit 2
Bias[2]
(0)
ADJ[2]
(0)
Gain[1]
(0)
SetPhs
[2] (1)
MUDEL[
3] (1)]
Guard
[2] (0)
Bit 1
MU_LOST (0)
Bit 1
RCVR_
LOOP_ON
(0)
LCKTHR[1]
(1)
Bit 1
RCVR_
LOOP_
ON (1)
LCKTHR[1]
(1)
Bit 1
Bias[1]
(0)
ADJ[1]
(0)
Gain[0]
(1)
SetPhs
[1] (1)
MUDEL
[2] (0)
Guard
[1] (1)
Bit 0
MU_LKD (1)
Bit 0
Bit 0
Bias[0]
(0)
ADJ[0]
(0)
Enable (1)
SetPhs[0]
(0)
MUDEL[1]
(0)
Guard[0]
(1)
Bit 0
RCVR_
CNT_
ENA (0)
LCKTHR[0]
(0)
RCVR_
CNT_ENA
(1)
LCKTHR[0]
(0)
Recommended
Value
0x30
0x80
0x03
0x46
0x6C
0xCB
Recommended
Value
0x01
Recommended
Value
0x70
0x42
Recommended
Value
0x50
0x42
AD9739