AD9649BCPZRL7-65 Analog Devices Inc, AD9649BCPZRL7-65 Datasheet - Page 29
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AD9649BCPZRL7-65
Manufacturer Part Number
AD9649BCPZRL7-65
Description
14 Bit 65 Msps ADC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9649BCPZRL7-20.pdf
(32 pages)
Specifications of AD9649BCPZRL7-65
Number Of Bits
14
Sampling Rate (per Second)
65M
Data Interface
Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
87.5mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-VFQFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9649BCPZRL7-65
Manufacturer:
AD
Quantity:
3 200
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
USR2 (Register 0x101)
Bit 3—Enable GCLK Detect
Normally set high, Bit 3 enables a circuit that detects encode
rates below ~5 MSPS. When a low encode rate is detected, an
internal oscillator, GCLK, is enabled, ensuring the proper oper-
ation of several circuits. If set low, the detector is disabled.
Rev. 0 | Page 29 of 32
Bit 2—Run GCLK
Bit 2 enables the GCLK oscillator. For some applications with
encode rates below 10 MSPS, it may be preferable to set this bit
high to supersede the GCLK detector.
Bit 0—Disable SDIO Pull-Down
Bit 0 can be set high to disable the internal 30 kΩ pull-down on
the SDIO pin, which can be used to limit the loading when many
devices are connected to the SPI bus.
AD9649