AD9629-40EBZ Analog Devices Inc, AD9629-40EBZ Datasheet - Page 23

• Manufacturer Part Number: AD9629-40EBZ
• Description: 12 Bit 40 Msps Low Pwr ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9629-40EBZ

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 40M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 60.5mW @ 40MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9629
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9629 includes a built-in self-test feature designed to
enable verification of the integrity of each channel as well as to
facilitate board level debugging. A built-in self-test (BIST) feature
that verifies the integrity of the digital datapath of the AD9629
is included. Various output test options are also provided to place
predictable values on the outputs of the AD9629.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9629 signal path. Perform the BIST test after a reset to ensure
the part is in a known state. During BIST, data from an internal
pseudorandom noise (PN) source is driven through the digital
datapath of both channels, starting at the ADC block output.
At the datapath output, CRC logic calculates a signature from
the data. The BIST sequence runs for 512 cycles and then stops.
Once completed, the BIST compares the signature results with a
predetermined value. If the signatures match, the BIST sets Bit 0
of Register 0x24, signifying the test passed. If the BIST test failed,
Bit 0 of Register 0x24 is cleared. The outputs are connected
during this test, so the PN sequence can be observed as it runs.
Writing 0x05 to Register 0x0E runs the BIST. This enables the Bit 0
(BIST enable) of Register 0x0E and resets the PN sequence
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generator, Bit 2 (BIST INIT) of Register 0x0E. At the completion
of the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN
sequence can be continued from its last value by writing a 0 in
Bit 2 of Register 0x0E. However, if the PN sequence is not reset,
the signature calculation does not equal the predetermined
value at the end of the test. At that point, the user needs to rely
on verifying the output data.
OUTPUT TEST MODES
The output test options are described in Table 16 at Address
0x0D. When an output test mode is enabled, the analog section
of the ADC is disconnected from the digital back-end blocks
and the test pattern is run through the output formatting block.
Some of the test patterns are subject to output formatting, and
some are not. The PN generators from the PN sequence tests
can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These
tests can be performed with or without an analog signal (if
present, the analog signal is ignored), but they do require an
encode clock. For more information, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
AD9629