AD962711-105EBZ Analog Devices Inc, AD962711-105EBZ Datasheet
AD962711-105EBZ
Specifications of AD962711-105EBZ
Related parts for AD962711-105EBZ
AD962711-105EBZ Summary of contents
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FEATURES SNR = 65.8 dBc (66.8 dBFS MHz @ 105 MSPS SFDR = 85 dBc to 70 MHz @ 105 MSPS Low power: 600 mW @ 105 MSPS SNR = 65.7 dBc (66.7 dBFS MHz @ ...
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AD9627-11 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications ..................................................................................... 5 ADC DC Specifications—AD9627BCPZ11-105/ AD9627BCPZ11-150 ................................................................... 5 ADC AC Specifications—AD9627BCPZ11-105/ AD9627BCPZ11-150 ...
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REVISION HISTORY 9/09—Rev Rev. A Changes to Table 4 ............................................................................ 9 Changes to Figure 3 ......................................................................... 11 Changes to Figure 11, Figure 12, and Figure 14 .......................... 17 Changes to Table 12 ........................................................................ 29 Changes to Configuration Using ...
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AD9627-11 GENERAL DESCRIPTION The AD9627- dual, 11-bit, 105 MSPS/150 MSPS analog-to- digital converter (ADC). The AD9627-11 is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, ...
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SPECIFICATIONS ADC DC SPECIFICATIONS—AD9627BCPZ11-105/AD9627BCPZ11-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, ...
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AD9627-11 ADC AC SPECIFICATIONS—AD9627BCPZ11-105/AD9627BCPZ11-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, ...
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DIGITAL SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, ...
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AD9627-11 Parameter Input Resistance Input Capacitance DIGITAL OUTPUTS CMOS Mode—DRVDD = 3.3 V High Level Output Voltage μ 0 Low Level Output Voltage μA ...
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SWITCHING SPECIFICATIONS—AD9627BCPZ11-105/AD9627BCPZ11-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input ...
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AD9627-11 TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK setup time SSYNC t SYNC to rising edge of CLK hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data ...
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CLK+ CLK– CH A/CH B DATA A N – A/CH B FAST A DETECT N – 7 DCO+ DCO– Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 001 Through Fast ...
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AD9627-11 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter ELECTRICAL AVDD, DVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND CML to ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS D10B (MSB) D0A (LSB) DNC = DO NOT CONNECT Table 8. Pin Function Descriptions (Parallel CMOS Mode) Pin No. Mnemonic Type ADC Power Supplies 20, 64 DRGND Ground 1, 21 DRVDD Supply 24, 57 DVDD ...
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AD9627-11 Pin No. Mnemonic Type Digital Outputs 15 D0A (LSB) Output 16 D1A Output 17 D2A Output 18 D3A Output 19 D4A Output 22 D5A Output 23 D6A Output 25 D7A Output 26 D8A Output 27 D9A Output 28 D10A ...
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D0– (LSB) D0+ (LSB) DNC = DO NOT CONNECT Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic Type ADC Power Supplies 20, 64 DRGND Ground 1, 21 DRVDD Supply 24, 57 DVDD Supply 36, 45, 46 ...
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AD9627-11 Pin No. Mnemonic Type Digital Outputs 7 D0+ (LSB) Output 6 D0− (LSB) Output 9 D1+ Output 8 D1− Output 13 D2+ Output 12 D2− Output 15 D3+ Output 14 D3− Output 17 D4+ Output 16 D4− Output 19 ...
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EQUIVALENT CIRCUITS VIN Figure 8. Equivalent Analog Input Circuit AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 9. Equivalent Clock Input Circuit DRVDD DRGND Figure 10. Digital Output DRVDD DVDD 26kΩ 1kΩ SDIO/DCS Figure 11. Equivalent SDIO/DCS or SMI SDFS Circuit CLK– ...
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AD9627-11 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, sample rate = 150 MSPS, DCS enabled, 1.0 V internal reference p-p differential input, VIN = −1.0 dBFS; and 64k sample, T ...
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SNR = 63.8dB (64.5dBFS) –20 ENOB = 10.2 BITS SFDR = 71.0dBc –40 SECOND –60 HARMONIC THIRD –80 HARMONIC –100 –120 FREQUENCY (MHz) Figure 22. AD9627-11-150 Single-Tone FFT with ...
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AD9627-11 120 100 SFDR (dBFS SNR (dBFS) 40 SFDR (dBc) 20 SNR (dBc) 0 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 28. AD9627-11-150 Single-Tone SNR/SFDR vs. Input Amplitude (A with f = 2.4 MHz IN ...
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SFDR (dBc) –40 IMD3 (dBc) –60 SFDR (dBFS) –80 –100 IMD3 (dBFS) –120 –90 –78 –66 –54 –42 INPUT AMPLITUDE (dBFS) Figure 34. AD9627-11-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A with f = 169.1 MHz 172.1 ...
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AD9627- – – – OUTPUT CODE Figure 40. AD9627-11 Grounded Input Histogram 0.2 0.1 0 –0.1 –0.2 0 256 512 768 1024 1280 OUTPUT CODE Figure ...
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THEORY OF OPERATION The AD9627-11 dual ADC design can be used for diversity recep- tion of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent ...
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AD9627-11 The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9627-11 (see Figure 46), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. ...
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VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9627-11. The input range can be adjusted by varying the reference voltage applied to the AD9627-11, using either the internal reference or an externally applied reference voltage. The ...
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AD9627-11 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac- teristics. Figure 54 shows the typical drift characteristics of the internal reference in 1.0 ...
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CLOCK INPUT AD951x LVDS DRIVER 0.1µF CLOCK INPUT 50kΩ 50kΩ Figure 59. Differential LVDS Sample Clock (Up to 625 MHz) In some applications, it may be acceptable to drive the sample clock inputs with a single-ended CMOS signal. In ...
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AD9627-11 The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9627-11. Power supplies for clock drivers should be sepa- rated from the ADC output driver supplies to ...
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The output data format can be selected for either offset binary or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 12). As detailed in Application Note AN-877, Interfacing to High Speed ADCs ...
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AD9627-11 ADC OVERRANGE AND GAIN CONTROL In receiver applications desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overflow indicator provides after-the-fact infor- mation on the state of the ...
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When the fast detect mode select bits are set to 0b001, 0b010, or 0b011, a subset of the fast detect output pins is available. In these modes, the fast detect output pins have a latency of six clock cycles. Table ...
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AD9627-11 Increment Gain (IG) and Decrement Gain (DG) The increment gain and decrement gain indicators are intended to be used together to provide information to enable external gain control. The decrement gain indicator works in conjunction with the coarse upper ...
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SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor com- putes the rms input magnitude, the peak magnitude, and/or the number of samples by which the magnitude exceeds a ...
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AD9627-11 Figure 67 illustrates the rms magnitude monitoring logic. FROM MEMORY MAP SIGNAL MONITOR DOWN IS COUNT = 1? PERIOD REGISTER COUNTER LOAD FROM CLEAR LOAD INPUT SIGNAL MONITOR PORTS ACCUMULATOR REGISTER (SMR) Figure 67. ADC Input RMS Magnitude Monitoring ...
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DC Correction Bandwidth The dc correction circuit is a high-pass filter with a programmable bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS). The bandwidth is controlled by writing the 4-bit dc correction register located at Register 0x10C, ...
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AD9627-11 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9627-11 includes built-in test features designed to enable verification of the integrity of each channel as well as facilitate board level debugging. A BIST (built-in self-test) feature is included that verifies the ...
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CHANNEL/CHIP SYNCHRONIZATION The AD9627-11 has a SYNC input that offers the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful for guaranteeing synchro- nized sample clocks across multiple ADCs. The signal monitor block ...
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AD9627-11 SERIAL PORT INTERFACE (SPI) The AD9627-11 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and ...
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CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin, and the SMI SCLK/PDWN pin serve as standalone CMOS- compatible control pins. When the device ...
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AD9627-11 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit loca- tions. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); ...
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MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 22 are not currently supported for this device. Table 22. Memory Map Registers Addr Register Bit 7 (Hex) Name (MSB) Bit 6 Chip Configuration Registers ...
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AD9627-11 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0E BIST Enable Open Open (Local) 0x10 Offset Adjust Open Open (Local) 0x14 Output Mode Drive Output strength type 3 CMOS CMOS or 1 ...
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Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x109 Fine Lower Open Open Threshold Register 1 (Local) 0x10A Increase Gain Dwell Time Register 0 (Local) 0x10B Increase Gain Dwell Time Register 1 (Local) 0x10C Signal Monitor Open DC DC ...
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AD9627-11 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x117 Signal Monitor Result Channel A Register 1 (Global) 0x118 Signal Monitor Open Open Result Channel A Register 2 (Global) 0x119 Signal Monitor Result Channel B Register 0 (Global) 0x11A ...
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Increase Gain Dwell Time (Register 0x10A and Register 0x10B) Register 0x10A, Bits[7:0]—Increase Gain Dwell Time[7:0] Register 0x10B, Bits[7:0]—Increase Gain Dwell Time[15:8] These registers are programmed with the dwell time in ADC clock cycles for which the signal must be below ...
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AD9627-11 Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits[7:0]—Signal Monitor Period[7:0] Register 0x114, Bits[7:0]—Signal Monitor Period[15:8] Register 0x115, Bits[7:0]—Signal Monitor Period[23:16] This 24-bit value sets the number of clock cycles over which the signal monitor performs its ...
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APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9627- system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power ...
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AD9627-11 EVALUATION BOARD The AD9627-11 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a double balun configuration (default) or optionally through the ...
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DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9627-11 evaluation board. POWER Connect the switching power supply that is provided in the evaluation kit between a ...
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AD9627-11 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION This section provides a brief description of the alternative analog input drive configuration using the AD8352. When using this particular drive option, some additional components need to be populated. For more details on the ...
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SCHEMATICS M OH 10K R41 100 R127 4.12K R126 DNP R36 24 24.9 R29 R35 F Figure 73. Evaluation Board Schematic, Channel A Analog Inputs Rev Page AD9627-11 07054-073 ...
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AD9627- 10K R53 D AMPVD M OH 100 R129 4.12K R128 DNP R68 M OH 24.9 OHM 24.9 R134 R135 F Figure 74. Evaluation Board Schematic, Channel B Analog Inputs Rev Page 07054-074 ...
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M OH 10K M OH 10K R85 R82 Figure 75. Evaluation Board Schematic, DUT Clock Input TP2 R83 DNP R34 57 57.6 R30 ...
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AD9627- VS_OUT67_ 50 2 VS_OUT67_ 51 V VS_OUT01_DI 52 OUT1B 53 OUT1 54 VS_OUT01_DRV 55 OUT0B 56 OUT0 57 VS_REF 4.12K 58 RSET_CLOCK R12 59 GND_REF 60 VS_PRESCALER 61 2 VS_PLL_ 5.1K 62 CP_RSET R11 63 REFINB 64 ...
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RES040 M OH 10K R105 2 RES040 M OH 10K R103 2 RES040 M OH 10K R102 2 RES040 M OH 10K R100 M OH 24.9 R87 TP1 RES060 M OH 57.6 R45 2 Figure 77. ...
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AD9627-11 DVDD 8 RPAK FD0A 1 16 FD1A 2 15 FD2A 3 14 FD3A PWR_SD PWR_SCL PWR_SDFS 8 9 RES040 R112 17 D2A ...
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RES040 M OH 10K R118 VAL R130 2 RES040 M OH 10K R140 Figure 79. Evaluation Board Schematic, Digital Output Interface Rev Page AD9627-11 07054-079 M OH 100 R77 ...
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AD9627-11 Figure 80. Evaluation Board Schematic, SPI Circuitry Rev Page 07054-080 2 RES040 OHM 10K R65 ...
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M KOH 140 R13 GND 4 1 RES0603 M OH 261 A C R16 CR7 SJ35 2 1 S2A_REC T Figure 81. Evaluation Board Schematic, Power Supply Rev Page 07054-081 M KOH 78.7 R14 1 ...
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AD9627- SJ36 SJ37 M KOH 140 Figure 82. Evaluation Board Schematic, Power Supply (Continued) Rev Page 07054-082 M KOH 78.7 5 ...
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EVALUATION BOARD LAYOUTS Figure 83. Evaluation Board Layout, Primary Side Rev Page AD9627-11 ...
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AD9627-11 Figure 84. Evaluation Board Layout, Ground Plane Rev Page ...
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Figure 85. Evaluation Board Layout, Power Plane Rev Page AD9627-11 ...
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AD9627-11 Figure 86. Evaluation Board Layout, Power Plane Rev Page ...
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Figure 87. Evaluation Board Layout, Ground Plane Rev Page AD9627-11 ...
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AD9627-11 Figure 88. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page ...
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Figure 89. Evaluation Board Layout, Silkscreen, Primary Side Rev Page AD9627-11 ...
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AD9627-11 Figure 90. Evaluation Board Layout, Silkscreen, Secondary Side Rev Page ...
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BILL OF MATERIALS Table 23. Evaluation Board Bill of Materials (BOM) Reference Item Qty Designator Description 1 1 AD9627-11CE_REVB PCB C3, C6, C7, C13, 0.1 μ ceramic C14, C17, C18, C20 to capacitor, SMT ...
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AD9627-11 Reference Item Qty Designator Description 29 3 R19, R20, R21 1 kΩ, 0603, 1/ resistor 30 9 R26, R27, R43, R46, 33 Ω, 0402, 1/16 W, R47, R70, R71, R73, 5% resistor R74 31 5 R57, R59 ...
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... TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9627BCPZ11-150 −40°C to +85°C 1 AD9627BCPZ11-105 −40°C to +85°C 1 AD962711-150EBZ 1 AD962711-105EBZ RoHS Compliant Part. 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 BSC BSC SQ 0.50 0. 0.30 0.80 MAX ...
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AD9627-11 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07054-0-9/09(A) Rev Page ...