AD9609BCPZRL7-80 Analog Devices Inc, AD9609BCPZRL7-80 Datasheet - Page 7
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AD9609BCPZRL7-80
Manufacturer Part Number
AD9609BCPZRL7-80
Description
10 Bit 80 Msps Low Pwr ADC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9609BCPZ-20.pdf
(32 pages)
Specifications of AD9609BCPZRL7-80
Number Of Bits
10
Sampling Rate (per Second)
80M
Data Interface
Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
92mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-VFQFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
OUT-OF-RANGE RECOVERY TIME
1
2
Conversion rate is the clock rate after the CLK divider.
Wake-up time is dependent on the value of the decoupling capacitors.
Input Clock Rate
Conversion Rate
CLK Period—Divide-by-1 Mode (t
CLK Pulse Width High (t
Aperture Delay (t
Aperture Uncertainty (Jitter, t
Data Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Skew (t
Pipeline Delay (Latency)
Wake-Up Time
Standby
2
1
A
)
CLK+
CLK–
DATA
DCO
SKEW
VIN
CH
)
)
PD
DCO
)
)
J
)
CLK
)
N – 1
t
CH
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
t
PD
Min
3
50/25
N
AD9609-20/AD9609-40
Figure 2. CMOS Output Data Timing
t
t
A
CLK
t
DCO
t
SKEW
N – 8
Typ
25.0/12.5
1.0
0.1
3
3
0.1
8
350
600/400
2
Rev. 0 | Page 7 of 32
N + 1
N – 7
N + 2
Max
625
20/40
N – 6
Min
3
15.38
N + 3
AD9609-65
Typ
7.69
1.0
0.1
3
3
0.1
8
350
300
2
N – 5
N + 4
Max
625
65
Min
3
12.5
N – 4
N + 5
AD9609-80
Typ
6.25
1.0
0.1
3
3
0.1
8
350
260
2
Max
625
80
AD9609
Unit
MHz
MSPS
ns
ns
ns
ps rms
ns
ns
ns
Cycles
μs
ns
Cycles