AD9609BCPZ-65 Analog Devices Inc, AD9609BCPZ-65 Datasheet - Page 6

10 Bit 65 Msps Low Pwr ADC

AD9609BCPZ-65

Manufacturer Part Number
AD9609BCPZ-65
Description
10 Bit 65 Msps Low Pwr ADC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9609BCPZ-65

Number Of Bits
10
Sampling Rate (per Second)
65M
Data Interface
Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
78mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-VFQFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9609
DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN)
LOGIC INPUTS (CSB)
DIGITAL OUTPUTS
1
2
Internal 30 kΩ pull-down.
Internal 30 kΩ pull-up.
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DRVDD = 3.3 V
DRVDD = 1.8 V
High Level Output Voltage, I
High Level Output Voltage, I
Low Level Output Voltage, I
Low Level Output Voltage, I
High Level Output Voltage, I
High Level Output Voltage, I
Low Level Output Voltage, I
Low Level Output Voltage, I
2
OL
OL
OL
OL
OH
OH
OH
OH
= 1.6 mA
= 50 μA
= 1.6 mA
= 50 μA
= 50 μA
= 0.5 mA
= 50 μA
= 0.5 mA
1
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Rev. 0 | Page 6 of 32
Min
0.2
GND − 0.3
−10
−10
8
1.2
0
−50
−10
1.2
0
−10
40
3.29
3.25
1.79
1.75
AD9609-20/AD9609-40/AD9609-65/AD9609-80
Typ
CMOS/LVDS/LVPECL
0.9
10
4
30
2
26
2
Max
3.6
AVDD + 0.2
+10
+10
12
DRVDD + 0.3
0.8
−75
+10
DRVDD + 0.3
0.8
+10
135
0.2
0.05
0.2
0.05
Unit
V
V p-p
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
V
V
V
V
V
V

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