AD9601BCPZ-200 Analog Devices Inc, AD9601BCPZ-200 Datasheet
AD9601BCPZ-200
Specifications of AD9601BCPZ-200
Related parts for AD9601BCPZ-200
AD9601BCPZ-200 Summary of contents
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FEATURES SNR = 59.4 dBFS @ MHz @ 250 MSPS IN ENOB of 9 MHz @ 250 MSPS (−1.0 dBFS) IN SFDR = 81 dBc @ MHz ...
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AD9601 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching ...
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SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN unless otherwise noted. Table 1. 1 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT ...
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AD9601 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 2. 2 Parameter SNR MHz MHz IN SINAD MHz ...
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DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 3. 1 Parameter CLOCK INPUTS Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Voltage (V ...
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AD9601 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 4. Parameter (Conditions) Maximum Conversion Rate Minimum Conversion Rate CLK+ Pulse Width High ( CLK+ Pulse Width Low ( ...
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TIMING DIAGRAMS N CLK+ CLK– DCO– DCO DAX N – CLK CLK+ CLK– DCO+ DCO– t PDA DAX DBX N – ...
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AD9601 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD Dx0 Through Dx9 to DRGND DCO+/DCO− to DRGND OVRA/OVRB to DGND CLK+ to AGND CLK− to AGND VIN+ to AGND ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 7. Single Data Rate Mode Pin Function Descriptions Pin No. Mnemonic 30, 32, 33, 34, 37, 38, 39, AVDD 41, 42, 43 24, 47 DRVDD 1 0 AGND 1 8, 23, 48 ...
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AD9601 Pin No. Mnemonic 4 DA7 5 DA8 6 DA9 (MSB) 10, 11, 51, 52 NIC 9 OVRA 12 DB0 (LSB) 13 DB1 14 DB2 15 DB3 16 DB4 17 DB5 18 DB6 19 DB7 20 DB8 21 DB9 (MSB) ...
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EQUIVALENT CIRCUITS AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 5. Clock Inputs AVDD VIN+ BUF 2kΩ BUF AVDD 2kΩ VIN– BUF Figure 6. Analog Inputs (V CML 1kΩ SCLK/DFS RESET 30kΩ PDWN Figure 7. Equivalent SCLK/DFS, RESET, PDWN Input Circuit CLK– ...
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AD9601 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, T otherwise noted. 0 –20 –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 11. AD9601-200 ...
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OUTPUT CODE Figure 17. AD9601-200 INL; 200 MSPS 400 350 300 TOTAL POWER (mW) 250 200 150 I (mA) AVDD 100 I ...
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AD9601 0 250MSPS 170.3MHz @ –1.0dBFS –20 SNR: 59.1dB ENOB: 9.60 BITS SFDR: 73dBc –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 23. AD9601-250 64k Point Single-Tone FFT; 250 MSPS, 170.3 MHz 70k 60k 50k ...
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OUTPUT CODE Figure 29. AD9601-250 DNL; 250 MSPS 90 SFDR SNR 125 175 ...
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AD9601 THEORY OF OPERATION The AD9601 architecture consists of a front-end sample-and- hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The quantized outputs from each stage are combined into a final 10-bit result in the digital correction logic. ...
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CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9601 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ pin and the CLK− pin via a transformer or capacitors. These ...
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AD9601 Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR for a full-scale input signal at a given input frequency (f ) due only to aperture jitter (t ...
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TIMING—SINGLE PORT MODE In single port mode, the CMOS output data is available from Data Port A (DA0 to DA9). The outputs for Port B (DB0 to DB9) are unused, and are high impedance in this mode. The Port A ...
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AD9601 LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS When connecting power to the AD9601 recommended that two separate supplies be used: one for analog (AVDD, 1.8 V nominal) and one for digital (DRVDD, 1.8 V nominal). If only a ...
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HARDWARE INTERFACE The pins described in Table 8 comprise the physical interface between the user’s programming device and the serial port of the AD9601. All serial pins are inputs, which is an open-drain output and should be tied to an ...
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AD9601 Table 10. Serial Timing Definitions Parameter Timing (minimum, ns CLK EN_SDIO t 5 DIS_SDIO Table 11. Output ...
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MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: chip configuration register map (Address 0x00 to Address 0x02), transfer register map (Address ...
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AD9601 Addr Bit 7 (Hex) Parameter Name (MSB) Bit 6 09 clock test_io OF ain_config output_mode output_phase Output 0 clock polarity 1 = inverted 0 = normal (default) 17 flex_output_delay Output ...
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EVALUATION BOARD SDIO_ODM SCLK_DTP D9B D2B D10B 18 53 D1B D10 19 52 D11B D0B D11 21 50 DORB DCO 22 49 DOR DCOB 23 48 GND ...
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AD9601 100PF 0.1UF C71 C73 0.1UF 0.1UF C72 C70 0.1UF 0.1UF C69 C65 0.1UF C68 0.1UF 0.1UF C64 C67 0.1UF 0.1UF C63 C66 0.1UF 0.1UF C62 C13 0.1UF 0.1UF C27 C59 0.1UF C28 0.1UF C60 0.1UF C29 0.1UF C30 0.1UF ...
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DNP C76 DNP L10 L11 DNP C45 C44 DNP DNP GND E13 E14 E12 DNP DNP C41 C40 R47 R36 00 00 Figure 47. AD9601 Evaluation Board Schematic Page R63 R65 R67 R69 R71 ...
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AD9601 Table 13. Bill of Materials Reference Qty Designator Package 1 PCB 7 C1, C3, C4, C5, 603 C6, C7, C10 6 C8, C9, C11, 6032-28 C12, C14, C55 1 C17 402 7 C27, C32, C33, 402 C62, C63, C64, ...
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Reference Qty Designator Package 2 R5, R6 402 2 R7, R16 402 6 R10, R11, R13, 402 R24, R25, R27 4 402 R12, R18, R19, R26, 7 R15, C16, C18, 402 C19, C20, R89, R90 4 RN1, RN2, RN3, 0402x8 ...
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AD9601 Reference Qty Designator Package 0 R3, R14, R33, 402 R34, R35, R48, R49 0 R42, R43, R54, 402 R85, R86 0 R28, R29, R30, 402 R31, R32 0 R37, R38 402 0 R39, R45 402 0 R58, R59 402 ...
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... OUTLINE DIMENSIONS BSC SQ PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9601BCPZ-200 −40°C to +85°C 1 AD9601BCPZ-250 −40°C to +85°C 1 AD9601-250EBZ RoHS Compliant Part. 8.00 0.60 MAX 0.60 MAX 43 42 TOP 7.75 VIEW BSC SQ ...
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AD9601 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07100-0-11/07(0) Rev Page ...