AD9600ABCPZ-125 Analog Devices Inc, AD9600ABCPZ-125 Datasheet - Page 12

• Manufacturer Part Number: AD9600ABCPZ-125
• Description: 10Bit 125Msps Dual 1.8V PB Free ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9600ABCPZ-125

• Number Of Bits: 10
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 800mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9600
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
ELECTRICAL
ENVIRONMENTAL
1
2
3
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The output data pins are D0A/D0B to D9A/D9B for the CMOS configuration
and D0+/D0− to D9+/D9− for the LVDS configuration.
The fast detect output pins are FD0A/FD0B to FD3A/FD3B for the CMOS
configuration and FD0+/FD0− to FD3+/FD3−.
The data clock output pins are DCOA and DCOB for the CMOS configuration
and DCO+ and DCO− for the LVDS configuration.
AVDD, DVDD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
VIN + A/VIN + B, VIN − A/VIN − B to
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
CML to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to DRGND
SDIO/DCS to DRGND
SMI SDO/OEB
SMI SCLK/PDWN
SMI SDFS
Output Data Pins to DRGND
Fast Detect Output Pins to DRGND
Data Clock Output Pins to DRGND
Operating Temperature Range
Maximum Junction Temperature
Storage Temperature Range
(Ambient)
Under Bias
(Ambient)
AGND
1
3
2
Rating
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−3.9 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +150°C
Rev. B | Page 12 of 72
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.
Table 7. Thermal Resistance
Package Type
64-Lead, 9 mm × 9 mm
1
2
3
4
Typical θ
Airflow increases heat dissipation, effectively reducing θ
addition, metal (such as metal traces through holes, ground,
and power planes) that is in direct contact with the package
leads reduces the θ
ESD CAUTION
Per JEDEC 51-7 standard and JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per MIL-Std 883, Method 1012.1.
Per JEDEC JESD51-8 (still air).
LFCSP (CP-64-3,
CP-64-6)
JA
and θ
JC
are specified for a 4-layer board in still air.
JA
.
Airflow
Velocity
(m/s)
0
1.0
2.0
θ
18.8
16.5
15.8
JA
1, 2
θ
0.6
JC
1, 3
θ
6.0
JB
JA
1, 4
. In
Unit
°C/W
°C/W
°C/W