AD9522-3BCPZ Analog Devices Inc, AD9522-3BCPZ Datasheet - Page 10
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AD9522-3BCPZ
Manufacturer Part Number
AD9522-3BCPZ
Description
12- Channel Clock Generator With Integra
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9522-3BCPZ-REEL7.pdf
(84 pages)
Specifications of AD9522-3BCPZ
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.25GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
2GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9522-3BCPZ
Manufacturer:
Clare
Quantity:
438
Part Number:
AD9522-3BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9522-3
CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)
Table 7.
Parameter
LVDS ABSOLUTE PHASE NOISE
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVDS OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVDS OUTPUT ABSOLUTE TIME JITTER
VCO = 2250 MHz; Output = 750 MHz
VCO = 1985 MHz; Output = 662 MHz
VCO = 1720 MHz; Output = 573 MHz
VCO = 1966 MHz; LVDS = 245.76 MHz; PLL LBW = 55 kHz
VCO = 1720 MHz; LVDS = 122.88 MHz; PLL LBW = 55 kHz
VCO = 1720 MHz; LVDS = 61.44 MHz; PLL LBW = 55 kHz
VCO = 1866 MHz; LVDS = 155.52 MHz; PLL LBW = 1.8 kHz
VCO = 1720 MHz; LVDS = 122.88 MHz; PLL LBW = 1.8 kHz
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
Min
Typ
−58
−90
−116
−133
−147
−150
−62
−94
−118
−135
−148
−151
−70
−99
−123
−138
−149
−151
Rev. 0 | Page 10 of 84
Min
Min
Max
Typ
440
362
187
Typ
141
312
136
285
340
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Max
Max
Unit
fs rms
fs rms
Test Conditions/Comments
Internal VCO; VCO divider = 3; LVDS output and for
loop bandwidths < 1 kHz
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
Test Conditions/Comments
Application example based on a typical
setup where the reference source is jittery,
so a narrower PLL loop bandwidth is used;
reference = 19.44 MHz; R DIV = 162
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 200 kHz to 10 MHz
Test Conditions/Comments
Application example based on a typical
setup where the reference source is clean,
so a wider PLL loop bandwidth is used;
reference = 15.36 MHz; R DIV = 1
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz