AD9522-1/PCBZ Analog Devices Inc, AD9522-1/PCBZ Datasheet - Page 49

• Manufacturer Part Number: AD9522-1/PCBZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc

Specifications of AD9522-1/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9522-1
• Primary Attributes: 12 LVDS/24 CMOS Outputs, 2.4 GHz VCO
• Secondary Attributes: I²C & SPI Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PLL Power-Down
The PLL section of the AD9522 can be selectively powered
down. There are two PLL power-down modes set by
Register 0x010[1:0]: asynchronous and synchronous.
In asynchronous power-down mode, the device powers down as
soon as the registers are updated. In synchronous power-down
mode, the PLL power-down is gated by the charge pump to
prevent unwanted frequency jumps. The device goes into power-
down on the occurrence of the next charge pump event after the
registers are updated.
Distribution Power-Down
The distribution section can be powered down by writing
0x230[1] = 1b, which turns off the bias to the distribution section.
If the LVDS power-down mode is in normal operation (0b), it is
possible for a low impedance load on that LVDS output to draw
significant current during this power-down. If the LVDS power-
down mode is set to 1b, the LVDS output is not protected from
reverse bias and can be damaged under certain termination
conditions.
Rev. 0 | Page 49 of 84
Individual Clock Output Power-Down
Any of the clock distribution outputs can be put into power-
down mode by individually writing to the appropriate registers.
The register map details the individual power-down settings for
each output. These settings are found in Register 0x0F0[0] to
Register 0x0FB[0].
Individual Clock Channel Power-Down
Any of the clock distribution channels can be powered down
individually by writing to the appropriate registers. Powering
down a clock channel is similar to powering down an individual
driver, but it saves more power because the dividers are also
powered down. Powering down a clock channel also automatically
powers down the drivers connected to it. The register map
details the individual power-down settings for each output
channel. These settings are found in 0x192[2], 0x195[2],
0x198[2], and 0x19B[2].
AD9522-1