AD9517-4ABCPZ Analog Devices Inc, AD9517-4ABCPZ Datasheet - Page 14

• Manufacturer Part Number: AD9517-4ABCPZ
• Description: 12OutputClock Generator With 1.8 GHz VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9517-4ABCPZ

• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:12
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.8GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9517-4
POWER DISSIPATION
Table 17.
Parameter
POWER DISSIPATION, CHIP
POWER DELTAS, INDIVIDUAL FUNCTIONS
Power-On Default
Full Operation; CMOS Outputs at 229 MHz
Full Operation; LVDS Outputs at 200 MHz
PD Power-Down
PD Power-Down, Maximum Sleep
V
VCO Divider
REFIN (Differential)
REF1, REF2 (Single-Ended)
VCO
PLL
Channel Divider
LVPECL Channel (Divider Plus Output Driver)
LVPECL Driver
LVDS Channel (Divider Plus Output Driver)
LVDS Driver
CMOS Channel (Divider Plus Output Driver)
CMOS Driver (Second in Pair)
CMOS Driver (First in Second Pair)
Fine Delay Block
CP
Supply
Min
Typ
1.0
75
31
4
30
20
4
70
75
160
90
120
50
0
30
1.4
1.4
30
100
50
Rev. B | Page 14 of 80
Max
1.2
185
4.8
2.0
2.1
Unit
W
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
W
W
mW
mW
mW
mW
mW
mW
mW
Test Conditions/Comments
No clock; no programming; default register values;
does not include power dissipated in external resistors
PLL on; internal VCO = 2750 MHz; VCO divider = 2;
all channel dividers on; four LVPECL outputs @ 687.5 MHz;
eight CMOS outputs (10 pF load) @ 229 MHz; all fine delay on,
maximum current; does not include power dissipated in
external resistors
PLL on; internal VCO = 2800 MHz, VCO divider = 2;
all channel dividers on; four LVPECL outputs @ 700 MHz;
four LVDS outputs @ 200 MHz; all fine delay on, maximum
current; does not include power dissipated in external resistors
PD pin pulled low; does not include power dissipated in
terminations
PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b;
SYNC power-down, Register 0x230[2] = 1b; REF for distribution
power-down, Register 0x230[1] = 1b
PLL operating; typical closed-loop configuration
Power delta when a function is enabled/disabled
VCO divider not used
All references off to differential reference enabled
All references off to REF1 or REF2 enabled; differential
reference not enabled
CLK input selected to VCO selected
PLL off to PLL on, normal operation; no reference enabled
Divider bypassed to divide-by-2 to divide-by-32
No LVPECL output on to one LVPECL output on
Second LVPECL output turned on, same channel
No LVDS output on to one LVDS output on
Second LVDS output turned on, same channel
Static; no CMOS output on to one CMOS output on
Static; second CMOS output, same pair, turned on
Static; first output, second pair, turned on
Delay block off to delay block enabled; maximum current setting