AD9517-3ABCPZ Analog Devices Inc, AD9517-3ABCPZ Datasheet - Page 4
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AD9517-3ABCPZ
Manufacturer Part Number
AD9517-3ABCPZ
Description
12OutputClock Generator With 2.0 GHz VCO
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9517-3ABCPZ-RL7.pdf
(80 pages)
Specifications of AD9517-3ABCPZ
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
1:12
Differential - Input:output
Yes/Yes
Frequency - Max
2.25GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LFCSP
Frequency-max
2.25GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9517-3ABCPZ-RL7
Manufacturer:
SAMTEC
Quantity:
2 000
AD9517-3
SPECIFICATIONS
Typical (typ) is given for V
unless otherwise noted. Minimum (min) and maximum (max) values are given over full V
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
V
V
V
RSET Pin Resistor
CPRSET Pin Resistor
BYPASS Pin Capacitor
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON-CHIP)
REFERENCE INPUTS
PHASE/FREQUENCY DETECTOR (PFD)
S
S_LVPECL
CP
PFD Input Frequency
Antibacklash Pulse Width
Frequency Range
VCO Gain (K
Tuning Voltage (V
Frequency Pushing (Open Loop)
Phase Noise @ 100 kHz Offset
Phase Noise @ 1 MHz Offset
Differential Mode (REFIN, REFIN)
Dual Single-Ended Mode (REF1, REF2)
Input Capacitance
Input Frequency
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Input Frequency (AC-Coupled)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled)
Input Logic High
Input Logic Low
Input Current
VCO
)
T
)
S
= V
S_LVPECL
= 3.3 V ± 5%; V
Min
3.135
2.375
V
2.7
Min
1750
0.5
1.35
1.30
4.4
0
2.0
−100
0
4.0
20
S
Typ
3.3
4.12
5.1
220
Typ
50
1
−108
−126
250
1.60
1.50
4.8
5.3
0.8
2
1.3
2.9
6.0
S
≤ V
Max
3.465
V
5.25
Max
2250
V
0.5
250
1.75
1.60
5.9
6.4
250
250
0.8
+100
100
45
CP
S
CP
Rev. B | Page 4 of 80
≤ 5.25 V; T
−
Unit
nF
Unit
MHz
dBc/Hz
dBc/Hz
mV p-p
V
V
μA
MHz
ns
V
V
V
kΩ
kΩ
MHz/V
V
MHz/V
MHz
V
kΩ
kΩ
MHz
MHz
V p-p
V
pF
MHz
ns
ns
A
= 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ,
Test Conditions/Comments
3.3 V ± 5%
Nominally 2.5 V to 3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);
actual current can be calculated by CP_lsb = 3.06/CPRSET;
connect to ground
Bypass for internal LDO regulator; necessary for LDO stability;
connect to ground
Test Conditions/Comments
See Figure 15
See Figure 10
V
the CP spurs may increase due to CP up/down mismatch
f = 2000 MHz
f = 2000 MHz
Differential mode (can accommodate single-ended input
by ac grounding undriven input)
Frequencies below about 1 MHz should be dc-coupled;
be careful to match V
PLL figure of merit increases with increasing slew rate;
see Figure 14
Self-bias voltage of REFIN
Self-bias voltage of REFIN
Self-biased
Self-biased
Two single-ended CMOS-compatible inputs
Slew rate > 50 V/μs
Slew rate > 50 V/μs; CMOS levels
Should not exceed V
Each pin, REFIN/REFIN (REF1/REF2)
Antibacklash pulse width = 1.3 ns, 2.9 ns
Antibacklash pulse width = 6.0 ns
Register 0x017[1:0] = 01b
Register 0x017[1:0] = 00b; Register 0x17[1:0] = 11b
Register 0x017[1:0] = 10b
CP
≤ V
S
when using internal VCO; outside of this range,
S
and T
1
1
A
(−40°C to +85°C) variation.
CM
S
p-p
(self-bias voltage)
1
1