AD9517-3A/PCBZ Analog Devices Inc, AD9517-3A/PCBZ Datasheet - Page 10
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AD9517-3A/PCBZ
Manufacturer Part Number
AD9517-3A/PCBZ
Description
12-Output Clock Generator With 2.8GHz VC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9517-3ABCPZ-RL7.pdf
(80 pages)
Specifications of AD9517-3A/PCBZ
Main Purpose
Timing, Clock Generator
Embedded
No
Utilized Ic / Part
AD9517-3A
Primary Attributes
2 Inputs, 12 Outputs, 2.0GHz VCO
Secondary Attributes
CMOS, LVPECL & LVDS Compatible
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9517-3
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
VCO = 1.97 GHz; LVPECL = 245.76 MHz; PLL LBW = 143 kHz
VCO = 1.97 GHz; LVPECL = 122.88 MHz; PLL LBW = 143 kHz
VCO = 1.97 GHz; LVPECL = 61.44 MHz; PLL LBW = 143 kHz
VCO = 1.87 GHz; LVPECL = 622.08 MHz; PLL LBW = 125 Hz
VCO = 1.87 GHz; LVPECL = 155.52 MHz; PLL LBW = 125 Hz
VCO = 1.97 GHz; LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
Rev. B | Page 10 of 80
Min
Min
Min
400
390
485
Typ
129
303
135
302
179
343
Typ
Typ
54
77
109
79
114
163
124
176
259
Max
Max
Max
Unit
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Unit
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Unit
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Test Conditions/Comments
Application example based on a typical
setup where the reference source is clean,
so a wider PLL loop bandwidth is used;
reference = 15.36 MHz; R = 1
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Application example based on a typical
setup where the reference source is jittery,
so a narrower PLL loop bandwidth is used;
reference = 10.0 MHz; R = 20
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Application example based on a typical
setup using an external 245.76 MHz VCXO
(Toyocom TCO-2112); reference = 15.36 MHz;
R = 1
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz