AD9517-2A/PCBZ Analog Devices Inc, AD9517-2A/PCBZ Datasheet - Page 6
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AD9517-2A/PCBZ
Manufacturer Part Number
AD9517-2A/PCBZ
Description
12-Output Clock Generator With 2.8GHz VC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9517-2ABCPZ-RL7.pdf
(80 pages)
Specifications of AD9517-2A/PCBZ
Main Purpose
Timing, Clock Generator
Embedded
No
Utilized Ic / Part
AD9517-2A
Primary Attributes
2 Inputs, 12 Outputs, 2.2GHz VCO
Secondary Attributes
CMOS, LVPECL & LVDS Compatible
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9517-2
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
1
CLOCK OUTPUTS
Table 4.
Parameter
LVPECL CLOCK OUTPUTS
LVDS CLOCK OUTPUTS
CMOS CLOCK OUTPUTS
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match V
OUT4, OUT5, OUT6, OUT7
OUT0, OUT1, OUT2, OUT3
Input Frequency
Input Sensitivity, Differential
Input Common-Mode Range, V
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
OUT4A, OUT4B, OUT5A, OUT5B,
OUT6A, OUT6B, OUT7A, OUT7B
Input Level, Differential
Input Common-Mode Voltage, V
Output Frequency, Maximum
Output High Voltage (V
Output Low Voltage (V
Output Differential Voltage (V
Output Frequency
Differential Output Voltage (V
Delta V
Output Offset Voltage (V
Delta V
Short-Circuit Current (I
Output Frequency
Output Voltage High (V
Output Voltage Low (V
OD
OS
SA
OL
OH
, I
)
OL
OS
OH
)
SB
)
)
)
)
OD
OD
CMR
CM
)
)
Min
0
0
1.3
1.3
3.9
Min
2950
V
V
550
247
1.125
V
1
1
S
S
S
− 1.12
− 2.03
− 0.1
Typ
150
1.57
150
4.7
2
Typ
V
V
790
360
1.24
14
S
S
− 0.98
− 1.77
Rev. B | Page 6 of 80
Max
2.4
1.6
2
1.8
1.8
5.7
Max
V
V
980
800
454
25
1.375
25
24
250
0.1
S
S
− 0.84
− 1.49
CM
.
Unit
GHz
GHz
mV p-p
V p-p
V
V
mV p-p
kΩ
pF
Unit
MHz
V
V
mV
MHz
mV
mV
V
mV
mA
MHz
V
V
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider)
Distribution only (VCO divider bypassed)
Measured at 2.4 GHz; jitter performance is improved
with slew rates > 1 V/ns
Larger voltage swings may turn on the protection
diodes and may degrade jitter performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
Test Conditions/Comments
Termination = 50 Ω to V
Differential (OUT, OUT)
Using direct to output; see Figure 25
Differential termination 100 Ω @ 3.5 mA
Differential (OUT, OUT)
The AD9517 outputs toggle at higher frequencies,
but the output amplitude may not meet the V
specification
V
the default amplitude setting with output driver not
toggling; see Figure 26 for variation over frequency
This is the absolute value of the difference
between V
when the complementary output is high
(V
This is the absolute value of the difference
between V
when the complementary output is high
Output shorted to GND
Single-ended; termination = 10 pF
See Figure 27
@ 1 mA load
@ 1 mA load
OH
OH
− V
+ V
OL
OL
measurement across a differential pair at
)/2 across a differential pair
OD
OS
when the normal output is high vs.
when the normal output is high vs.
S
− 2 V
OD