AD9517-1BCPZ Analog Devices Inc, AD9517-1BCPZ Datasheet - Page 27
![12-Output Clock Generator With 2.5GHz VC](/photos/6/50/65022/cp-48-8_sml.jpg)
AD9517-1BCPZ
Manufacturer Part Number
AD9517-1BCPZ
Description
12-Output Clock Generator With 2.5GHz VC
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9517-1ABCPZ-RL7.pdf
(80 pages)
Specifications of AD9517-1BCPZ
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
1:12
Differential - Input:output
Yes/Yes
Frequency - Max
2.65GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LFCSP
Frequency-max
2.65GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9517-1/PCBZ - BOARD EVAL FOR AD9517-1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
The AD9517 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Table 52 and Table 53 through Table 62). Each section or
function must be individually programmed by setting the
appropriate bits in the corresponding control register or registers.
High Frequency Clock Distribution—CLK or External
VCO > 1600 MHz
The AD9517 power-up default configuration has the PLL
powered off and the routing of the input set so that the
CLK/ CLK input is connected to the distribution section
through the VCO divider (divide-by-2/ divide-by-3/divide-by-4/
divide-by-5/divide-by-6). This is a distribution-only mode that
allows for an external input up to 2400 MHz (see
maximum frequency that can be applied to the channel dividers
is 1600 MHz; therefore, higher input frequencies must be
divided down before reaching the channel dividers. This input
routing can also be used for lower input frequencies, but the
minimum divide is 2 before the channel dividers.
When the PLL is enabled, this routing also allows the use of the
PLL with an external VCO or VCXO with a frequency of less
than 2400 MHz. In this configuration, the internal VCO is not
used and is powered off. The external VCO/VCXO feeds
directly into the prescaler.
The register settings shown in Table 21 are the default values of
these registers at power-up or after a reset operation. If the
contents of the registers are altered by prior programming after
power-up or reset, these registers can also be set intentionally to
these values.
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
Table 3
). The
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Table 21. Default Settings of Some PLL Registers
Register
0x010[1:0] = 01b
0x1E0[2:0] = 010b
0x1E1[0] = 0b
0x1E1[1] = 0b
When using the internal PLL with an external VCO, the PLL
must be turned on.
Table 22. Settings When Using an External VCO
Register
0x010[1:0] = 00b
0x010 to 0x01E
0x1E1[1] = 0b
An external VCO requires an external loop filter that must be
connected between CP and the tuning pin of the VCO. This
loop filter determines the loop bandwidth and stability of the
PLL. Make sure to select the proper PFD polarity for the VCO
being used.
Table 23. Setting the PFD Polarity
Register
0x010[7] = 0b
0x010[7] = 1b
Function
PLL asynchronous power-down (PLL off ).
Set VCO divider = 4.
Use the VCO divider.
CLK selected as the source.
Function
PLL normal operation (PLL on).
PLL settings. Select and enable a reference
input; set R, N (P, A, B), PFD polarity, and I
according to the intended loop configuration.
CLK selected as the source.
Function
PFD polarity positive (higher control voltage
produces higher frequency).
PFD polarity negative (higher control voltage
produces lower frequency).
AD9517-1
CP
,