AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 33

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Automatic/Internal Holdover Mode
When enabled, the automatic/internal holdover mode auto-
matically puts the charge pump into a high impedance state
when the loop loses lock. The assumption is that the only reason
that the loop loses lock is due to the PLL losing the reference
clock; therefore, the holdover function puts the charge pump
into a high impedance state to maintain the VCO frequency as
close as possible to the original frequency before the reference
clock disappeared.
A flowchart of the internal/automatic holdover function
operation is shown in Figure 40.
HIGH IMPEDANCE
HIGH IMPEDANCE
WHEN DLD WENT
LD PIN == HIGH
CHARGE PUMP
CHARGE PUMP
EDGE AT PFD?
PLL ENABLED
DLD == HIGH
DLD == LOW
REFERENCE
RELEASE
LOW?
WAS
YES
YES
YES
YES
YES
Figure 40. Flowchart of Automatic/Internal Holdover Mode
NO
NO
NO
NO
YES
Rev. 0 | Page 33 of 76
LOOP OUT OF LOCK. DIGITAL LOCK
DETECT SIGNAL GOES LOW WHEN THE
LOOP LEAVES LOCK AS DETERMINED
BY THE PHASE DIFFERENCE AT THE
INPUT OF THE PFD.
ANALOG LOCK DETECT PIN INDICATES
LOCK WAS PREVIOUSLY ACHIEVED.
(0x1D[3] = 1: USE LD PIN VOLTAGE
WITH HOLDOVER.
0x1D[3] = 0: IGNORE LD PIN VOLTAGE,
TREAT LD PIN AS ALWAYS HIGH.)
CHARGE PUMP IS MADE
HIGH IMPEDANCE.
PLL COUNTERS CONTINUE
OPERATING NORMALLY.
CHARGE PUMP REMAINS HIGH
IMPEDANCE UNTIL THE REFERENCE
HAS RETURNED.
TAKE CHARGE PUMP OUT OF
HIGH IMPEDANCE. PLL CAN
NOW RESETTLE.
WAIT FOR DLD TO GO HIGH. THIS TAKES
5 TO 255 CYCLES (PROGRAMMING OF THE DLD
DELAY COUNTER) WITH THE REFERENCE AND
FEEDBACK CLOCKS INSIDE THE LOCK WINDOW AT
THE PFD. THIS ENSURES THAT THE HOLDOVER
FUNCTION WAITS FOR THE PLL TO SETTLE AND LOCK
BEFORE THE HOLDOVER FUNCTION CAN BE
RETRIGGERED.
The holdover function senses the logic level of the LD pin as a
condition to enter holdover. The signal at LD can be from the
DLD, ALD, or current source digital LD (CSDLD) mode. It is
possible to disable the LD comparator (0x01D[3]), which causes
the holdover function to always sense LD as being high. If DLD
is used, it is possible for the DLD signal to chatter while the PLL
is reacquiring lock. The holdover function may retrigger, thereby
preventing the holdover mode from terminating. Use of the
current source lock detect mode is recommended to avoid this
situation (see the Current Source Digital Lock Detect section).
When in holdover mode, the charge pump stays in a high
impedance state as long as there is no reference clock present.
AD9516-5