AD9516-2BCPZ-REEL7 Analog Devices Inc, AD9516-2BCPZ-REEL7 Datasheet - Page 12
![IC,Ten Distributed-Output Clock Driver,LLCC,64PIN,PLASTIC](/photos/6/50/65021/505-64-lfcsp_sml.jpg)
AD9516-2BCPZ-REEL7
Manufacturer Part Number
AD9516-2BCPZ-REEL7
Description
IC,Ten Distributed-Output Clock Driver,LLCC,64PIN,PLASTIC
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9516-2BCPZ-REEL7.pdf
(80 pages)
Specifications of AD9516-2BCPZ-REEL7
Pll
Yes
Input
Clock
Output
CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
1:14
Differential - Input:output
Yes/Yes
Frequency - Max
2.33GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
2.33GHz
Function
Clock Generator
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
LFCSP EP
Pin Count
64
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9516-2/PCBZ - BOARD EVAL FOR AD9516-2 2.2GHZ
Lead Free Status / Rohs Status
Compliant
AD9516-2
DELAY BLOCK ADDITIVE TIME JITTER
Table 13.
Parameter
DELAY BLOCK ADDITIVE TIME JITTER
1
SERIAL CONTROL PORT
Table 14.
Parameter
CS (INPUT)
SCLK (INPUT)
SDIO (WHEN INPUT)
SDIO, SDO (OUTPUTS)
TIMING
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
100 MHz Output
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Output Logic 1 Voltage
Output Logic 0 Voltage
Clock Rate (SCLK, 1/t
Pulse Width High, t
Pulse Width Low, t
SDIO to SCLK Setup, t
SCLK to SDIO Hold, t
SCLK to Valid SDIO and SDO, t
CS to SCLK Setup and Hold, t
CS Minimum Pulse Width High, t
Delay (1600 μA, 0x1C) Fine Adj. 000000
Delay (1600 μA, 0x1C) Fine Adj. 101111
Delay (800 μA, 0x1C) Fine Adj. 000000
Delay (800 μA, 0x1C) Fine Adj. 101111
Delay (800 μA, 0x4C) Fine Adj. 000000
Delay (800 μA, 0x4C) Fine Adj. 101111
Delay (400 μA, 0x4C) Fine Adj. 000000
Delay (400 μA, 0x4C) Fine Adj. 101111
Delay (200 μA, 0x1C) Fine Adj. 000000
Delay (200 μA, 0x1C) Fine Adj. 101111
Delay (200 μA, 0x4C) Fine Adj. 000000
Delay (200 μA, 0x4C) Fine Adj. 101111
LOW
HIGH
DH
SCLK
DS
)
S
, t
DV
H
PWH
1
Min
Min
2.0
2.0
2.0
2.7
16
16
2
1.1
2
3
Typ
110
2
110
2
10
20
2
Typ
0.54
0.60
0.65
0.85
0.79
1.2
1.2
2.0
1.3
2.5
1.9
3.8
Rev. A | Page 12 of 80
Max
0.8
3
0.8
1
0.8
0.4
25
8
Max
Unit
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
Unit
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
nA
nA
pF
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
SCLK has an internal 30 kΩ pull-down resistor
Test Conditions/Comments
Incremental additive jitter
CS has an internal 30 kΩ pull-up resistor