AD9510/PCBZ Analog Devices Inc, AD9510/PCBZ Datasheet - Page 20

• Manufacturer Part Number: AD9510/PCBZ
• Description: 800MHz PLL Clock Dist Eval Bd.
• Manufacturer: Analog Devices Inc

Specifications of AD9510/PCBZ

• Main Purpose: Timing, Clock Distribution
• Utilized Ic / Part: AD9510
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9510
Table 13. Pin Function Descriptions
Pin No.
1
2
3, 7, 8, 12, 22,
27, 32, 49, 50,
55, 62
4, 9, 13, 23, 26,
30, 31, 33, 36,
37, 40, 41, 44,
45, 48, 51, 52,
56, 59, 60, 64
5
6
10
11
14
15
16
17
18
19
20
21
24
25
28
29
34
35
38
39
42
43
46
47
53
54
57
58
61
63
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be attached to ground, GND.
REFIN
REFINB
GND
VS
VCP
CP
CLK2
CLK2B
CLK1
CLK1B
FUNCTION
STATUS
SCLK
SDIO
SDO
CSB
OUT7B
OUT7
OUT3B
OUT3
OUT2B
OUT2
OUT6B
OUT6
OUT5B
OUT5
OUT4B
OUT4
OUT1B
OUT1
OUT0B
OUT0
RSET
CPRSET
Mnemonic
Description
PLL Reference Input.
Complementary PLL Reference Input.
Ground.
Power Supply (3.3 V) V
Charge Pump Power Supply VCP
for VCOs requiring extended tuning range.
Charge Pump Output.
Clock Input Used to Connect External VCO/VCXO to Feedback Divider, N. CLK2 also drives the distribution
section of the chip and may be used as a generic clock input when PLL is not used.
Complementary Clock Input Used in Conjunction with CLK2.
Clock Input that Drives Distribution Section of the Chip.
Complementary Clock Input Used in Conjunction with CLK1.
Multipurpose Input May Be Programmed as a Reset (RESETB), Sync (SYNCB), or Power-Down (PDB) Pin.
This pin is internally pulled down by a 30 kΩ resistor. If this pin is left NC, the part is in reset by default.
To avoid this, connect this pin to V
Output Used to Monitor PLL Status and Sync Status.
Serial Data Clock.
Serial Data I/O.
Serial Data Output.
Serial Port Chip Select.
Complementary LVDS/Inverted CMOS Output.
LVDS/CMOS Output.
Complementary LVPECL Output.
LVPECL Output.
Complementary LVPECL Output.
LVPECL Output.
Complementary LVDS/Inverted CMOS Output. OUT6 includes a delay block.
LVDS/CMOS Output. OUT6 includes a delay block.
Complementary LVDS/Inverted CMOS Output. OUT5 includes a delay block.
LVDS/CMOS Output. OUT5 includes a delay block.
Complementary LVDS/Inverted CMOS Output.
LVDS/CMOS Output.
Complementary LVPECL Output.
LVPECL Output.
Complementary LVPECL Output.
LVPECL Output.
Current Set Resistor to Ground. Nominal value = 4.12 kΩ.
Charge Pump Current Set Resistor to Ground. Nominal value = 5.1 kΩ.
S
.
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S
. It should be greater than or equal to V
S
with a 1 kΩ resistor.
S
. VCP
S
may be set as high as 5.5 V