AD9467-200EBZ Analog Devices Inc, AD9467-200EBZ Datasheet - Page 27

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AD9467-200EBZ

Manufacturer Part Number
AD9467-200EBZ
Description
16 BIT 200 MSPS ADC EVAL
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9467-200EBZ

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SCLK
Table 12. Serial Timing Definitions
Parameter
t
t
t
t
t
t
t
t
t
SDIO
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
CSB
DON’T CARE
DON’T CARE
Timing (Minimum, ns)
5
2
40
5
2
16
16
10
10
t
S
R/W
t
DS
W1
W0
t
DH
A12
t
HIGH
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 68)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 68)
A11
A10
t
LOW
Figure 68. Serial Timing Details
A9
Rev. B | Page 27 of 32
t
CLK
A8
A7
D5
D4
D3
D2
D1
D0
t
H
DON’T CARE
AD9467
DON’T CARE

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