AD9381KSTZ-150 Analog Devices Inc, AD9381KSTZ-150 Datasheet - Page 16

• Manufacturer Part Number: AD9381KSTZ-150
• Description: IC,TV/VIDEO CIRCUIT,Video Interface Circuit,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Analog Devices Inc

AD9381
Hex
Address
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
Read/Write
or Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read
Read
Read/Write
Read/Write
Read/Write
Read/Write
Bits
[2:0]
[7:2]
[1:0]
[7:0]
[3:0]
[7:0]
[3:0]
[7:0]
[7]
[6:5]
[4:0]
[6]
[5]
[4]
[3]
[2:0]
[6]
[5]
[4]
[3:0]
[7:4]
[3:0]
[7]
[6]
[5:0]
[7]
[6]
[5:0]
[7:6]
[5]
Default Value
*****000
011000**
******01
00000100
****0101
00000000
****0010
11010000
0*******
*00*****
***11000
*0******
**0*****
***0****
****0***
*****000
*0******
**0*****
***0****
****0000
1001****
****0110
0*******
*0******
**001101
1*******
*0******
**010101
10******
**0*****
Register Name
Interlace Offset
VS Delay
HS Delay MSB
HS Delay
Line Width MSB
Line Width
Screen Height MSB
Screen Height
Ctrl EN
I2S Out Mode
I2S Bit Width
TMDS Sync Detect
TMDS Active
AV Mute
HDCP Keys Read
HDMI Quality
HDMI Content Encrypted
DVI HSYNC Polarity
DVI VSYNC Polarity
HDMI Pixel Repetition
MV Pulse Max
MV Pulse Min
MV Oversample En
MV Pal En
MV Line Count Start
MV Detect Mode
MV Settings Override
MV Line Count End
MV Pulse Limit Set
Low Freq Mode
Rev. 0 | Page 16 of 44
Description
Sets the difference (in HSYNCs) in field length
between Field 0 and Field 1.
Sets the delay (in lines) from the VSYNC leading
edge to the start of active video.
MSB, Register 0x29.
Sets the delay (in pixels) from the HSYNC leading
edge to the start of active video.
MSB, Register 0x2B.
Sets the width of the active video line in pixels.
MSB, Register 0x2D.
Sets the height of the active screen in lines.
Allows Ctrl [3:0] to be output on the I
00 = I
01 = right-justified.
10 = left-justified.
11 = raw IEC60958 mode.
Sets the desired bit width for right-justified mode.
Detects a TMDS DE.
Detects a TMDS clock.
Gives the status of AV mute based on general
control packets.
Returns 1 when read of EEPROM keys is successful.
Returns quality number based on DE edges.
This bit is high when HDCP decryption is in use
(content is protected). The signal goes low when
HDCP is not being used. Customers can use this bit
to allow copying of the content. The bit should be
sampled at regular intervals because it can change
on a frame-by-frame basis.
Returns DVI HSYNC polarity.
Returns DVI VSYNC polarity.
Returns current HDMI pixel repetition amount.
0 = 1×, 1 = 2×, ... .The clock and data outputs
automatically de-repeat by this value.
Sets the maximum pseudo sync pulse width for
Macrovision® detection.
Sets the minimum pseudo sync pulse width for
Macrovision detection.
Tells the Macrovision detection engine whether we
are oversampling or not.
Tells the Macrovision detection engine to enter PAL
mode.
Sets the start line for Macrovision detection.
0 = standard definition.
1 = progressive scan mode.
0 = use hard-coded settings for line counts and
pulse widths.
1 = use I
Sets the end line for Macrovision detection.
Sets the number of pulses required in the last 3
lines (SD mode only).
Sets audio PLL to low frequency mode. Low
frequency mode should only be set for pixel clocks
<80 MHz.
2
S mode.
2
C values for these settings.
2
S data pins.