AD9266BCPZ-65 Analog Devices Inc, AD9266BCPZ-65 Datasheet - Page 10

• Manufacturer Part Number: AD9266BCPZ-65
• Description: 16 Bit, 65 MSPS 1.8V Single ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9266BCPZ-65

• Number Of Bits: 16
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 113mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9266
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Pin No.
0, Exposed Paddle
1, 2
3, 24, 29, 32
4
5
6
7 to 12
14 to 21
13
22
23
25
26
27
28
30, 31
Mnemonic
AGND
CLK+, CLK−
AVDD
CSB
SCLK/DFS
SDIO/PDWN
NC
D1_D0 (LSB) to
(MSB) D15_D14
DRVDD
DCO
MODE/OR
VREF
SENSE
VCM
RBIAS
VIN−, VIN+
Description
The exposed paddle is the only ground connection on the chip. It must be soldered to the analog
ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength
benefits.
Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs.
1.8 V Supply Pin for ADC Core Domain.
SPI Chip Select. Active low enable, 30 kΩ internal pull-up.
SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.
Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.
DFS high = twos complement output; DFS low = offset binary output.
SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.
Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-
down. See Table 14 for details.
No Connect.
ADC Digital Outputs.
1.8 V to 3.3 V Supply Pin for Output Driver Domain.
Data Clock Digital Output.
Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR).
Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1).
Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0).
Chip power-down (SPI Register 0x08, Bits[7:5] = 100b).
Chip standby (SPI Register 0x08, Bits[7:5] = 101b).
Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b).
Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b).
Out-of-range (OR) digital output only in non-SPI mode.
1.0 V Voltage Reference Input/Output. See Table 10.
Reference Mode Selection. See Table 10.
Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.
Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
ADC Analog Inputs.
NOTES
1.
2. THE EXPOSED PADDLE (PIN 0) IS THE ONLY GND
SDIO/PDWN
NC = NO CONNECT.
CONNECTION ON THE CHIP AND MUST BE CONNECTED
TO THE PCB AGND.
SCLK/DFS
AVDD
CLK+
CLK–
CSB
NC
NC
1
2
3
4
5
6
7
8
Figure 3. Pin Configuration
Rev. 0 | Page 10 of 32
(Not to Scale)
AD9266
TOP VIEW
24
23
22
21
20
19
18
17
AVDD
MODE/OR
DCO
(MSB) D15_D14
D13_D12
D11_D10
D9_D8
D7_D6