AD9235BCP-40EBZ Analog Devices Inc, AD9235BCP-40EBZ Datasheet - Page 3

• Manufacturer Part Number: AD9235BCP-40EBZ
• Description: 12-BIT 3V 20/40/65 MSPS ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9235BCP-40EBZ

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 40M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 180mW @ 40MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9235-40
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DIGITAL SPECIFICATIONS
Parameter
LOGIC INPUTS
LOGIC OUTPUTS*
DRVDD = 3.3 V
DRVDD = 2.5 V
*Output voltage levels measured with 5 pF load on each output.
Specifications subject to change without notice.
REV. B
SWITCHING SPECIFICATIONS
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
OUT-OF-RANGE RECOVERY
NOTES
1
2
3
Specifications subject to change without notice.
For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models.
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
High-Level Output Voltage
High-Level Output Voltage
Low-Level Output Voltage
Low-Level Output Voltage
High-Level Output Voltage
High-Level Output Voltage
Low-Level Output Voltage
Low-Level Output Voltage
TIME
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulsewidth High
CLK Pulsewidth Low
Output Delay
Pipeline Delay (Latency)
Aperture Delay (t
Aperture Uncertainty Jitter (t
Wake-Up Time
(IOH = 50 µA)
(IOH = 0.5 mA)
(IOL = 1.6 mA)
(IOL = 50 µA)
(IOH = 50 µA)
(IOH = 0.5 mA)
(IOL = 1.6 mA)
(IOL = 50 µA)
2
(t
3
PD
A
)
)
1
1
J
)
Temp Level
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Temp Level
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
ANALOG
INPUT
DATA
OUT
CLK
Test
IV
IV
IV
IV
V
IV
IV
IV
IV
IV
IV
IV
IV
Test
VI
V
V
V
V
V
V
V
V
V
V
N–9
N–1
Figure 1. Timing Diagram
–10
–10
3.29
3.25
2.49
2.45
Min
2.0
20
50.0
15.0
15.0
Min
AD9235BRU-20
N–8
AD9235BRU-20
N
N–7
t A
Typ
2
Typ
3.5
7
1.0
0.5
3.0
1
N+1
–3–
N–6
N+2
Max
0.8
+10
+10
0.2
0.05
0.2
0.05
Max
1
N–5
N+3
2.0
–10
–10
3.29
3.25
2.49
2.45
Min
40
25.0
8.8
8.8
Min
N–4
AD9235BRU-40
AD9235BRU-40
N+4
t
PD
N–3
Typ
2
N+5
Typ
3.5
7
1.0
0.5
3.0
1
= 6.0ns MAX
2.0ns MIN
N–2
N+6
Max
0.8
+10
+10
0.2
0.05
0.2
0.05
Max
1
N–1
N+7
AD9235BRU/BCP-65
AD9235BRU/BCP-65
Min
2.0
–10
–10
3.29
3.25
2.49
2.45
Min
65
15.4
6.2
6.2
N
N+8
Typ
2
Typ
3.5
7
1.0
0.5
3.0
2
Max
0.8
+10
+10
0.2
0.05
0.2
0.05
Max
1
AD9235
Unit
V
V
µA
µA
pF
V
V
V
V
V
V
V
V
Unit
MSPS
MSPS
ns
ns
ns
ns
Cycles
ns
ps rms
ms
Cycles