AD9229BCPZ-65 Analog Devices Inc, AD9229BCPZ-65 Datasheet - Page 20

• Manufacturer Part Number: AD9229BCPZ-65
• Description: IC,A/D CONVERTER,QUAD,12-BIT,CMOS,LLCC,48PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9229BCPZ-65

• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial
• Number Of Converters: 4
• Power Dissipation (max): 1.47W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9229-65EBZ - BOARD EVALUATION FOR AD9229
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9229
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (f
calculated with the following equation:
In the equation, the rms aperture jitter, t
sum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Applications that require undersampling are particularly
sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9229. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the
last step.
Power Dissipation and Power-Down Mode
As shown in Figure 40 and Figure 41, the power dissipated by
the AD9229 is proportional to its sample rate. The digital power
dissipation does not vary much because it is determined
primarily by the DRVDD supply and bias current of the LVDS
output drivers.
Figure 40. Supply Current vs. f
1200
1100
1000
SNR degradation = 20 × log 10 [1/2 × π × f
900
800
700
600
10
15
A
) due only to aperture jitter (t
20
TOTAL POWER
I
I
DRVDD
AVDD
25
ENCODE (MSPS)
SAMPLE
30
for f
IN
= 10.3 MHz, f
35
A
, represents the root
40
A
SAMPLE
A
× t
) can be
45
A
]
= 50 MSPS
50
350
300
250
200
150
100
50
0
Rev. B | Page 20 of 40
By asserting the PDWN pin high, the AD9229 is placed in
power-down mode. In this state, the ADC typically dissipates
3 mW. During power-down, the LVDS output drivers are placed
in a high impedance state. Reasserting the PDWN pin low
returns the AD9229 to normal operating mode.
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, PLL, and biasing
networks. The decoupling capacitors on REFT and REFB are
discharged when entering standby mode and then must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in the power-down
mode; shorter cycles result in proportionally shorter wake-up
times. With the recommended 0.1 μF and 10 μF decoupling
capacitors on REFT and REFB, it takes approximately 1 sec to
fully discharge the reference buffer decoupling capacitors and
4 ms to restore full operation.
Digital Outputs
The AD9229’s differential outputs conform to the ANSI-644
LVDS standard. To set the LVDS bias current, place a resistor
(RSET is nominally equal to 4.0 kΩ) to ground at the
LVDSBIAS pin. The RSET resistor current is derived on-chip
and sets the output current at each output equal to a nominal
3.5 mA. A 100 Ω differential termination resistor placed at the
LVDS receiver inputs results in a nominal 350 mV swing at the
receiver. To adjust the differential signal swing, simply change
the resistor to a different value, as shown in Table 7.
Table 7. LVDSBIAS Pin Configuration
RSET
3.7
4.0
4.3
Figure 41. Supply Current vs. f
1400
1300
1200
1100
1000
kΩ
kΩ
kΩ
900
800
(default)
10
20
I
TOTAL POWER
I
DRVDD
AVDD
30
Differential Output Swing
375 mV p-p
350 mV p-p
325 mV p-p
ENCODE (MSPS)
SAMPLE
for f
40
IN
= 10.3 MHz, f
50
SAMPLE
60
= 65 MSPS
500
450
400
350
300
250
200
150
100
50
0