AD9226ASTZ Analog Devices Inc, AD9226ASTZ Datasheet - Page 16
AD9226ASTZ
Manufacturer Part Number
AD9226ASTZ
Description
12-BIT 65 MSPS ADC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9226ASTZ.pdf
(28 pages)
Specifications of AD9226ASTZ
Rohs Compliant
YES
Number Of Bits
12
Sampling Rate (per Second)
65M
Data Interface
Parallel
Number Of Converters
3
Power Dissipation (max)
475mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9226-EB - BOARD EVAL FOR AD9226-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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AD9226
The same midsupply potential may be obtained from the
CMLEVEL pin of the AD9226 in the LQFP package.
Referring to Figure 7, a series resistor, R
AD9226 and the secondary of the transformer. The value of
33 ohm was selected to specifically optimize both the THD and
SNR performance of the ADC. R
help provide a low-pass filter to block high-frequency noise.
Transformers with other turns ratios may also be selected to
optimize the performance of a given application. For example, a
given input signal source or amplifier may realize an improve-
ment in distortion performance at reduced output power levels
and signal swings. By selecting a transformer with a higher
impedance ratio (e.g., Minicircuits T16-6T with a 1:16 imped-
ance ratio), the signal level is effectively “stepped up” thus
further reducing the driving requirements of signal source.
0V
49.9
MINICIRCUITS
–100
–120
–20
–40
–60
–80
0
T1-1T
0
1V p-p
49.9
0.1 F
1k
4
0.1 F
450
499
33
1k
R
S
8
33
R
S
1k
0.1 F
499
10 F
499
12
AVDD
AD8138
1k
MHz
16
S
15pF
and the internal capacitance
5V
VINA
VINB
S
AD9226
20
, is inserted between the
AVDD
VINB
VINA
SNR = 66.9dBc
SFDR = 70.0dBc
AD9226
CAPB
CAPT
10 F
0.1 F
24
CAPT
CAPB
0.1 F
28
0.1 F
0.1 F
0.1 F
0.1 F
32
10 F
10 F
0.1 F
SINGLE-ENDED DRIVER CIRCUITS
The AD9226 can be configured for single-ended operation using
dc- or ac-coupling. In either case, the input of the ADC must be
driven from an operational amplifier that will not degrade the
ADC’s performance. Because the ADC operates from a single
supply, it will be necessary to level-shift ground-based bipolar
signals to comply with its input requirements. Both dc- and
ac-coupling provide this necessary function, but each method
results in different interface issues which may influence the
system design and performance.
Single-ended operation requires that VINA be ac- or dc-coupled
to the input signal source, while VINB of the AD9226 be biased
to the appropriate voltage corresponding to the middle of the input
span. The single-ended specifications for the AD9226 are char-
acterized using Figure 9a circuitry with input spans of 1 V and
2 V. The common-mode level is 2.5 V.
If the analog inputs exceed the supply limits, internal parasitic
diodes will turn on. This will result in transient currents within
the device. Figure 8 shows a simple means of clamping an input.
It uses a series resistor and two diodes. An optional capacitor is
shown for ac-coupled applications. A larger series resistor can
be used to limit the fault current through D1 and D2. This
can cause a degradation in overall performance. A similar
clamping circuit can also be used for each input if a differen-
tial input signal is being applied. A better method to ensure
the input is not overdriven is to use amplifiers powered by a single
5 V supply such as the AD8138.
AC-COUPLING AND INTERFACE ISSUES
For applications where ac-coupling is appropriate, the op amp
output can be easily level-shifted by means of a coupling
capacitor. This has the advantage of allowing the op amp’s com-
mon-mode level to be symmetrically biased to its midsupply
level (i.e., (AVDD/2). Op amps that operate symmetrically with
respect to their power supplies typically provide the best ac
performance as well as greatest input/output span. Various high-
speed performance amplifiers that are restricted to +5 V/–5 V
operation and/or specified for 5 V single-supply operation can be
easily configured for the 2 V or 1 V input span of the AD9226.
Simple AC Interface
Figure 9a shows a typical example of an ac-coupled, single-
ended configuration of the SSOP package. The bias voltage
shifts the bipolar, ground-referenced input signal to approxi-
mately AVDD/2. The capacitors, C1 and C2, are 0.1 µF ceramic
and 10 µF tantalum capacitors in parallel to achieve a low
cutoff frequency while maintaining a low impedance over a
wide frequency range. The combination of the capacitor and the
resistor form a high-pass network with a high-pass –3 dB fre-
quency determined by the equation,
V
V
CC
EE
OPTIONAL
AC-COUPLING
CAPACITOR
f
–3 dB
= 1/(2 × π × R × (C1 + C2))
30
R
S1
AVDD
D2
D1
20
R
S2
AD9226