AD9223ARSZ Analog Devices Inc, AD9223ARSZ Datasheet
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AD9223ARSZ
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AD9223ARSZ Summary of contents
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FEATURES Monolithic 12-Bit A/D Converter Product Family Family Members Are: AD9221, AD9223, and AD9220 Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS, and 10.0 MSPS Low Power Dissipation: 59 mW, 100 mW, and 250 mW Single 5 V Supply Integral Nonlinearity ...
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AD9221/AD9223/AD9220–SPECIFICATIONS (AVDD = 5 V, DVDD = SPECIFICATIONS otherwise noted.) Parameter RESOLUTION MAX CONVERSION RATE INPUT REFERRED NOISE (TYP REF V = 2.5 V REF ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) ...
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V, DVDD SPECIFICATIONS Ended Input T Parameter MAX CONVERSION RATE DYNAMIC PERFORMANCE Input Test Frequency 1 (VINA = –0.5 dBFS) Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOBs) Signal-to-Noise Ratio (SNR) Total ...
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AD9221/AD9223/AD9220 SWITCHING SPECIFICATIONS Parameter Clock Period* CLOCK Pulsewidth High CLOCK Pulsewidth Low Output Delay Pipeline Delay (Latency) *The clock period may be extended without degradation in specified performance @ 25 °C. Specifications subject to change without notice. ...
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PIN CONFIGURATION 1 CLK 28 2 (LSB) BIT BIT 11 26 BIT AD9221/ BIT AD9223/ 6 AD9220 BIT BIT 7 22 TOP VIEW (Not to Scale) 8 BIT ...
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AD9221/AD9223/AD9220 AD9221–Typical Performance Characteristics 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4095 CODE TPC 1. Typical DNL 80 75 –0.5dB 70 –6.0dB –20.0dB 0.1 1.0 FREQUENCY – MHz TPC ...
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AD9223–Typical Performance Characteristics 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4095 CODE TPC 10. Typical DNL 80 75 –0.5dB 70 –6.0dB –20.0dB 0.1 1.0 10.0 FREQUENCY – MHz TPC ...
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AD9221/AD9223/AD9220 AD9220–Typical Performance Characteristics 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 1 4095 CODE TPC 19. Typical DNL 80 75 –0.5dB 70 –6dB –20dB 0.1 1.0 10.0 FREQUENCY – MHz ...
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INTRODUCTION The AD9221/AD9223/AD9220 are members of a high perfor- mance, complete single-supply 12-bit ADC product family based on the same CMOS pipelined architecture. The product family allows the system designer an upward or downward component selection path based on dynamic ...
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AD9221/AD9223/AD9220 The addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily config- ure the inputs for either single-ended operation ...
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Referring to Figure 5, the differential SHA is implemented using a switched-capacitor topology. Therefore, its input impedance and its subsequent effects on the input drive source should be understood to maximize the converter’s performance. The com- bination of the pin ...
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AD9221/AD9223/AD9220 shunt capacitor can help limit the wideband noise at the A/D’s input by forming a low-pass filter. Note, however, that the combination of this series resistance with the equivalent input capacitance of the AD9221/AD9223/AD9220 should be evalu- ated for ...
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Input Input Connection Coupling Span (V) VINA* Single-Ended × VREF × VREF 2.5 – VREF Single-Ended × VREF × VREF 5 2 × VREF 2.5 – ...
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AD9221/AD9223/AD9220 Reference Input Span (VINA–VINB) Operating Mode (V p-p) INTERNAL 2 INTERNAL 5 2 ≤ SPAN ≤ 5 and INTERNAL SPAN = 2 × VREF 2 ≤ SPAN ≤ 5 EXTERNAL (Nondynamic) 2 ≤ SPAN ≤ 5 EXTERNAL (Dynamic) DRIVING ...
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OPTIONAL AC COUPLING AVDD V CAPACITOR 1N4148 30 D1 1N4148 V EE Figure 12. Simple Clamping Circuit SINGLE-ENDED MODE OF OPERATION The AD9221/AD9223/AD9220 can be configured for single- ended operation using coupling. In ...
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AD9221/AD9223/AD9220 AC COUPLING AND INTERFACE ISSUES For applications where ac coupling is appropriate, the op amp’s output can be easily level shifted to the common-mode voltage, VCM, of the AD9221/AD9223/AD9220 via a coupling capacitor. This has the advantage of allowing ...
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AD828: Dual Version of AD818 Best Applications: Differential and/or Low Imped- ance Input Drivers, Low Noise, Gains ≥ +2 Limits: THD above 100 kHz AD812: Dual, 145 MHz Unity GBW, Single-Supply Cur- rent Feedback ± ...
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AD9221/AD9223/AD9220 –55 –65 AD9221 AD9223 –75 –85 – FREQUENCY – MHz Figure 18. AD9221/AD9223/AD9220 SFDR vs. Input Frequency ( p-p Input Span –0.5 dB) IN Figure 19 shows the schematic ...
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Shorting the VREF pin directly to the SENSE pin places the internal reference amplifier in unity-gain mode and the resultant VREF output Therefore, the valid input range However, shorting the SENSE ...
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AD9221/AD9223/AD9220 The AD9221/AD9223/AD9220 contains an internal reference buffer, A2 (see Figure 9), that simplifies the drive requirements of an external reference. The external reference must be able to drive a ≈5 kΩ (± 20%) load. Note that the bandwidth of ...
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Table truth table for the over/underrange circuit in Figure 28, which uses NAND gates. Systems requiring programmable gain conditioning of the AD9221/AD9223/ AD9220 input signal can immediately detect an out-of-range condition, thus eliminating gain ...
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AD9221/AD9223/AD9220 300 280 INPUT = 5V p-p 260 INPUT = 2V p-p 240 220 200 CLOCK FREQUENCY – MHz Figure 29c. AD9220 Power Consumption vs. Clock Frequency GROUNDING AND DECOUPLING Analog and Digital Grounding Proper ...
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APPLICATIONS Direct IF Down Conversion Using the AD9220 As previously noted, the AD9220’s performance in the differen- tial mode of operation extends well beyond its baseband region and into several Nyquist zone regions. Thus, the AD9220 may be well suited ...
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AD9221/AD9223/AD9220 The offset calibration circuitry consists of a DAC, U5 and the buffer amplifier, U4. The DAC is configured for a bipolar adjustment span of ± 64 LSB with a 1/2 LSB resolution span with respect to the AD9221/AD9223/AD9220. Note ...
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TPA D2 1N5711 VINA C19 0 C13 1N5711 15pF NOT C26 INSTALLED 0.1 F C24 C23 10 F 0.1 F TP1 16V A C28 C25 0.1 F 0.1 F +5A A TPB D4 ...
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AD9221/AD9223/AD9220 Figure 37. Evaluation Board Component Side Layout (Not to Scale) Figure 38. Evaluation Board Solder Side Layout (Not to Scale) –26– REV. E ...
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Figure 39. Evaluation Board Ground Plane Layout (Not to Scale) REV. E Figure 40. Evaluation Board Power Plane Layout –27– AD9221/AD9223/AD9220 ...
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AD9221/AD9223/AD9220 Figure 41. Evaluation Board Component Side Silkscreen (Not to Scale) Figure 42. Evaluation Board Component Side Silkscreen (Not to Scale) –28– REV. E ...
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COPLANARITY 0.10 2.00 MAX 0.05 MIN REV. E OUTLINE DIMENSIONS 28-Lead Standard SmWall Outline Package [SOIC] Wide Body (R-28) Dimensions shown in millimeters and (inches) 18.10 (0.7126) 17.70 (0.6969 7.60 (0.2992) 7.40 (0.2913) 1 ...
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AD9221/AD9223/AD9220 Revision History Location 2/03—Data Sheet changed from REV REV. E. Updated graphic captions . . . . . . . . . . . . . . . . . . . . . . . . ...
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