AD9222-65EBZ Analog Devices Inc, AD9222-65EBZ Datasheet - Page 28

• Manufacturer Part Number: AD9222-65EBZ
• Description: Octal 12 Bit, 65 MSPS Serial LVDS ADC EB
• Manufacturer: Analog Devices Inc

Specifications of AD9222-65EBZ

• Number Of Adc's: 8
• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial
• Inputs Per Adc: 2 Single
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 910mW @ 65MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9222
• Kit Application Type: Data Converter
• Application Sub Type: ADC
• Features: Serial LVDS, Data And Frame Clock Outputs, 325MHz Full-power Analog Bandwidth
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9222
on and Trace Lengths Greater than 24 Inches on Standard FR-4, AD9222-50
Figure 76. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Figure 77. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination
–100
–200
–300
–400
–100
–200
–300
–400
–500
400
300
200
100
500
400
300
200
100
140
120
100
–150ps
–1.5ns
–300ps
80
70
60
50
40
30
20
10
80
60
40
20
–1.5ns
Greater than 24 Inches on Standard FR-4, AD9222-65
0
0
0
0
EYE: ALL BITS
EYE: ALL BITS
–1.0ns
–200ps
–100ps
–1.0ns
–0.5ns
–100ps
–0.5ns
–50ps
0ns
0ps
0ps
0ns
0.5ns
100ps
0.5ns
50ps
ULS: 7591/15591
ULS: 12072/12072
200ps
100ps
1.0ns
1.0ns
300ps
1.5ns
150ps
1.5ns
Rev. D | Page 28 of 60
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the
Memory Map section.
Table 8. Digital Output Coding
Code
4095
2048
2047
0
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 780 Mbps
(12 bits × 65 MSPS = 780 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up via the SPI to allow
encode rates as low as 5 MSPS. See the Memory Map section to
enable this feature.
Figure 78. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination
on and Trace Lengths Greater than 24 Inches on Standard FR-4, AD9222-65
–100
–200
–300
–400
–500
(VIN + x) − (VIN − x),
Input Span = 2 V p-p (V)
+1.00
0.00
−0.000488
−1.00
500
400
300
200
100
140
120
100
–1.5ns
–200ps
80
60
40
20
0
0
EYE: ALL BITS
–1.0ns
–100ps
–0.5ns
0ps
0ns
Digital Output Offset Binary
(D11 ... D0)
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
100ps
0.5ns
ULS: 8000/15600
200ps
1.0ns
300ps
1.5ns