AD9216BCPZ-105 Analog Devices Inc, AD9216BCPZ-105 Datasheet
AD9216BCPZ-105
Specifications of AD9216BCPZ-105
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AD9216BCPZ-105 Summary of contents
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FEATURES Integrated dual 10-bit ADC Single 3 V supply operation SNR = 57.6 dBc (to Nyquist, AD9216-105) SFDR = 74 dBc (to Nyquist, AD9216-105) Low power: 150 mW/ch at 105 MSPS Differential input with 300 MHz 3 dB bandwidth Exceptional ...
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AD9216 TABLE OF CONTENTS DC Specifications ............................................................................. 3 AC Specifications.............................................................................. 4 Logic Specifications.......................................................................... 5 Switching Specifications .................................................................. 6 Timing Diagram ............................................................................... 7 Absolute Maximum Ratings............................................................ 8 Explanation of Test Levels ........................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. ...
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... V 3.0 25°C I -2.6 ±0.2 +2.6 -2.6 25°C I -0.4 ±0.1 +0.4 -0.4 25°C I -1.6 ±0.1 +1.6 -1.6 Rev Page AD9216 AD9216BCPZ-105 Typ Max Min Typ Max 10 Guaranteed Guaranteed ±0.3 +1.9 −2.2 ±0.3 +2.2 ±0.4 +1.6 −1.6 ±0.4 +1.6 ±0.4 +1.0 −1.0 ±0.5 +1.0 ± ...
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... V 78.5 25°C V 71.0 25°C V 70.0 25°C V 300 25°C V −80.0 Rev Page −0.5 dBFS differential input, 1.0 V internal reference, AD9216BCPZ-80 AD9216BCPZ-105 Min Typ Max Min Typ 58.5 58.0 55.9 58.1 54.8 57.6 56.4 58.5 56.4 57.6 58.0 57.4 57.5 57.3 58 ...
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... V internal reference, IN AD9216BCPZ-65 AD9216BCPZ-80 Min Typ Max Min 2.0 2.0 0.8 −10 +10 −10 −10 +10 −10 2 2.45 2.45 0.05 Rev Page AD9216 AD9216BCPZ-105 Typ Max Min Typ Max 2.0 0.8 0.8 +10 −10 +10 +10 −10 + 2.45 0.05 0.05 Unit V V µ ...
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... 15.4 VI 4.6 VI 4.6 I 4.5 6.4 I 2.0 V 1 1 parameters. Rev Page AD9216BCPZ-80 AD9216BCPZ-105 Min Typ Max Min Typ Max 80 105 10 10 12.5 9.5 4.4 3.8 4.4 3.8 4.5 6.4 4.5 6.4 2.0 2.0 1.0 1.0 1.0 1 1.5 1.5 0.5 ...
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TIMING DIAGRAM N–1 ANALOG INPUT CLK DATA N–8 OUT N+1 N N+2 N N+4 N–7 N–6 N–5 N–4 N–3 Figure 2. Rev Page N+8 N+7 N+6 N+5 N–2 N– ...
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AD9216 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs CLK_A, CLK_B, DCS, DFS, MUX_SELECT, OEB_A, OEB_B, SHARED_REF, PDWN_A, PDWN_B VIN−_A, VIN+_A, VIN−_B, VIN+_B REFT_A, REFB_A,VREF, REFT_B, REFB_B, SENSE 1 ENVIRONMENTAL Operating Temperature Junction Temperature Lead ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN+_A VIN–_A REFT_A REFB_A SENSE REFB_B REFT_B VIN–_B VIN+_B DNC = DO NOT CONNECT Table 7. Pin Function Descriptions Pin No. Mnemonic Description 13, 16 AGND Analog Ground. 2 VIN+_A Analog Input ...
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AD9216 Pin No. Mnemonic Description 46 to 51, D0_A (LSB) to Channel A Data Output Bits D9_A (MSB) 59 OEB_A Output Enable for Channel A. Logic 0 enables Data Bus A. Logic 1 sets outputs to High-Z. ...
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TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of ...
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AD9216 Noise (for Any Range within the ADC) This value includes both thermal and quantization noise. − ⎛ FS SNR ⎜ ⎜ = × × dBm .001 10 noise ⎝ where the input impedance. FS ...
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TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3.0 V, DRVDD = 2 25° –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 4. FFT 105 MSPS 10.3 MHz at ...
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AD9216 100 SNR 60 SINAD CLOCK FREQUENCY (MHz) Figure 10. SNR, SINAD, H2, H3, SFDR vs. Sample Clock Frequency MHz at −0.5 dBFS (−105 Grade) IN 100 90 ...
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SFDR dBFS 60 SFDR dBc 50 40 65dB REF. LINE 30 SNR –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) Figure 16. SFDR vs. Analog Input Level MHz ...
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AD9216 100 TWO-TONE SFDR dBFS 60 TWO-TONE SFDR dBc 70dB REF LINE –60 –50 –40 –30 TWO-TONE ANALOG INPUT LEVEL (dBFS) Figure 22. Two-Tone IMD Performance vs. Input Drive Level (100.1 ...
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SFDR SNR SINAD 55 –40 – TEMPERATURE (°C) Figure 28. SNR, SINAD, SFDR vs. Temperature, (−105 Grade MHz at −0.5 dBFS, 105 MSPS , External Reference Mode IN 80 ...
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AD9216 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 200 400 600 CODE Figure 34. Typical DNL Plot 10.3 MHz at −0.5 dBFS, 105 MSPS IN (−105 Grade) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 ...
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EQUIVALENT CIRCUITS AVDD VIN+_A, VIN–_A, VIN+_B, VIN–_B Figure 37. Equivalent Analog Input AVDD CLK_A, CLK_B DCS, DFS, MUX_SELECT, SHARED_REF Figure 38. Equivalent Clock, Digital Inputs Circuit PDWN Figure 39. Power-Down Input DRVDD Figure 40. Digital Outputs Rev Page ...
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AD9216 THEORY OF OPERATION The AD9216 consists of two high performance ADCs that are based on the AD9215 converter core. The dual ADC paths are independent, except for a shared internal band gap reference source, VREF. Each of the ADC ...
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For example p-p signal may be applied to VIN+, while reference is applied to VIN−. The AD9216 then accepts an input signal varying between 2 V and the single-ended configuration, distortion ...
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AD9216 CLOCK INPUT AND CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and result, may be sensitive to clock duty cycle. Commonly tolerance is required on the ...
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OUTPUT CODING Table 8. Code (VIN+) − (VIN−) Offset Binary 1023 > +0.998 V 11 1111 1111 1023 +0.998 V 11 1111 1111 1022 +0.996 V 11 1111 1110 • • • • • • 513 +0.002 V 10 0000 ...
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AD9216 VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the AD9216. The input range can be adjusted by varying the reference voltage applied to the AD9216, using either the inter- nal reference with different external ...
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External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve the thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may ...
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AD9216 DUAL ADC LFCSP PCB The PCB requires a low jitter clock source, analog sources, and power supplies. The PCB interfaces directly with ADI’s standard dual-channel data capture board (HSC-ADC-EVAL- DC), which together with ADI’s ADC Analyzer™ software allows for ...
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LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM) Table 12. Dual CSP PCB Rev. B No. Quan. Reference Designator C2, C5, C7, C9, C10, C22, C36 3 44 C4, C6, C8, C11 to C15, C20, ...
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AD9216 LFCSP PCB SCHEMATICS ENCA D7A D7_A 49 D8A D8_A 50 D9A D9_A 51 DRVDD2 52 DRGND2 53 D10A D10_A 54 D11A D11_A 55 D12A D12_A 56 D13A D13_A 57 OTRA OTR_A 58 OEB_A 59 PWDN_A 60 MUX_SEL 61 SH_REF ...
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Figure 52. PCB Schematic ( Rev Page AD9216 ...
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AD9216 ENCA ENCB Figure 53. PCB Schematic ( Rev Page ...
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LFCSP PCB LAYERS Figure 54. PCB Top-Side Silkscreen Rev Page AD9216 ...
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AD9216 Figure 55. PCB Top-Side Copper Routing Rev Page ...
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Figure 56. PCB Ground Layer Rev Page AD9216 ...
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AD9216 Figure 57. PCB Split Power Plane Rev Page ...
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Figure 58. PCB Bottom-Side Copper Routing Rev Page AD9216 ...
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AD9216 Figure 59. PCB Bottom-Side Silkscreen Rev Page ...
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THERMAL CONSIDERATIONS The AD9216 LFCSP package has an integrated heat slug that improves the thermal and electrical properties of the package when locally attached to a ground plane at the PCB. A thermal (filled) via array to a ground plane ...
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... Lead Frame Chip Scale Package (LFCSP-VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP-VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP-VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP-VQ) Evaluation Board with AD9216BCPZ-80 Evaluation Board with AD9216BCPZ-105 Rev Page 0.30 0.25 0.60 MAX ...
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NOTES Rev Page AD9216 ...
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AD9216 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04775–0–6/05(A) Rev Page ...