AD9211BCPZ-200 Analog Devices Inc, AD9211BCPZ-200 Datasheet - Page 23

• Manufacturer Part Number: AD9211BCPZ-200
• Description: IC,A/D CONVERTER,SINGLE,10-BIT,CMOS,LLCC,56PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9211BCPZ-200

• Number Of Bits: 10
• Sampling Rate (per Second): 200M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 356mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9211-300EBZ - BOARD EVALUATION FOR AD9211-300AD9211-250EBZ - BOARD EVAL FOR AD9211-250AD9211-200EBZ - BOARD EVAL FOR AD9211-200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9. Serial Port Pins
Mnemonic
SCLK
SDIO
CSB
RESET
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 51
and Table 11.
During an instruction phase, a 16-bit instruction is transmitted.
Data then follows the instruction phase and is determined by
the W0 and W1 bits, which is 1 or more bytes of data. All data is
composed of 8-bit words. The first bit of each individual byte of
serial data indicates whether this is a read or write command.
This allows the serial data input/output (SDIO) pin to change
direction from an input to an output.
Data may be sent in MSB or in LSB first mode. MSB first is
default on power-up and can be changed by changing the con-
figuration register. For more information about this feature and
others, see the AN-877, Interfacing to High Speed ADCs via SPI.
SCLK
SDIO
CSB
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Function
SCLK (Serial Clock) is the serial shift clock in.
SCLK is used to synchronize serial interface
reads and writes.
SDIO (Serial Data Input/Output) is a dual-purpose
pin. The typical role for this pin is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB (Chip Select Bar) is an active low control that
gates the read and write cycles.
Master Device Reset. When asserted, device
assumes default settings. Active low.
t
S
R/W
t
DS
W1
W0
t
DH
A12
A11
t
HI
Figure 51. Serial Port Interface Timing Diagram
A10
t
LO
A9
Rev. 0 | Page 23 of 28
t
CLK
A8
A7
HARDWARE INTERFACE
The pins described in Table 9 comprise the physical interface
between the user’s programming device and the serial port of
the AD9211. All serial pins are inputs with an open-drain
configuration and should be tied to an external pull-up or pull-
down resistor (suggested value of 10 kΩ).
This interface is flexible enough to be controlled by either
PROMS or PIC mirocontrollers as well. This provides the user
with an alternate method to program the ADC other than a SPI
controller.
If the user chooses not to use the SPI interface, some pins serve
a dual function and are associated with a specific function when
strapped externally to AVDD or ground during device power
on. The Configuration Without the SPI section describes the
strappable functions supported on the AD9230.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SPI SDIO/DCS and SPI SCLK/DFS pins can alternately
serve as standalone CMOS-compatible control pins. When the
device is powered up, it is assumed that the user intends to use
the pins as static control lines for the duty cycle stabilizer. In
this mode, the SPI CSB chip select should be connected to
ground, which disables the serial port interface.
Table 10. Mode Selection
Mnemonic
SPI SDIO/DCS
SPI SCLK/DFS
D5
D4
External
Voltage
AVDD
AGND
AVDD
AGND
D3
D2
Configuration
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
D1
D0
t
H
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AD9211
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