AD7896BR Analog Devices Inc, AD7896BR Datasheet - Page 8

• Manufacturer Part Number: AD7896BR
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD7896BR

• Package/case: 8-SOIC
• Features: +2.7V To 5V, 12?Bit ADC In 8?Pin
• Interface Type: Serial
• Leaded Process Compatible: No
• Number Of Bits: 12
• Number Of Channels: 1
• Peak Reflow Compatible (260 C): No
• Rohs Status: RoHS non-compliant
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 10.8mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-AD7896CBZ - BOARD EVALUATION FOR AD7896CBZ
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

OPERATING MODES
Mode 1 Operation (High Sampling Performance)
The timing diagram in Figure 2 is for optimum performance in
Operating Mode 1 where the falling edge of CONVST starts the
conversion and puts the track-and-hold amplifier into its hold
mode. This falling edge of CONVST also causes the BUSY
signal to go high to indicate that a conversion is taking place.
The BUSY signal goes low when the conversion is complete,
which is 8 µs max after the falling edge of CONVST, and new
data from this conversion is available in the output register of
the AD7896. A read operation accesses this data. This read
operation consists of 16 clock cycles, and the length of this read
operation depends on the serial clock frequency. For the fastest
throughput rate (with a serial clock of 10 MHz at 5 V opera-
tion), the read operation will take 1.6 µs. The read operation
must be complete at least 400 ns before the falling edge of
the next CONVST, which gives a total time of 10 µs for the full
throughput time (equivalent to 100 kHz). This mode of opera-
tion should be used for high sampling applications.
Mode 2 Operation (Auto Sleep after Conversion)
The timing diagram in Figure 3 is for optimum performance in
Operating Mode 2 where the part automatically goes into sleep
mode once BUSY goes low after conversion and “wakes up”
AD7896
CONVST
CONVST
SCLK
BUSY
Figure 3. Mode 2 Timing Diagram Where Automatic Sleep Function Is Initiated
BUSY
SCLK
TRACK-AND-HOLD GOES
Figure 2. Mode 1 Timing Operation Diagram for High Sampling Performance
CONVERSION IS
INITIATED AND
WAKES
INTO HOLD
PART
UP
t
1
t
1
CONVERSION
IS INITIATED
TRACK-AND-
HOLD GOES
INTO HOLD
t
t
CONVERT
t
CONVERT
CONVERT
= 8 s
= 8 s
= 14 s
CONVERSION ENDS
CONVERSION
14µs LATER
8 s LATER
ENDS
–8–
SERIAL READ
OPERATION
SERIAL READ
OPERATION
before the next conversion takes place. This is achieved by
keeping CONVST low at the end of conversion, whereas it was
high at the end of conversion for Mode 1 operation. The rising
edge of CONVST “wakes up” the part. This wake-up time is 6
µs, at which point the track-and-hold amplifier goes into its hold
mode. The conversion takes 8 µs after this, provided the
CONVST has gone low, giving a total of 14 µs from the rising
edge of CONVST to the conversion being complete, which is
indicated by the BUSY going low. Note that since the wake-
up time from the rising edge of CONVST is 6 µs, when the
CONVST pulsewidth is greater than 6 µs, the conversion will
take more than the 14 µs shown in the diagram from the rising
edge of CONVST. This is because the track-and-hold amplifier
goes into its hold mode on the falling edge of CONVST and
then the conversion will not be complete for a further 8 µs. In
this case, the BUSY will be the best indicator for when the
conversion is complete. Even though the part is in sleep mode,
data can still be read from the part. The read operation consists
of 16 clock cycles as in Mode 1 operation. For the fastest serial
clock of 10 MHz at 5 V operation, the read operation will take
1.6 µs, which must be complete at least 400 ns before the falling
edge of the next CONVST to allow the track-and-hold amplifier
to have enough time to settle. This mode is very useful when the
part is converting at a slow rate as the power consumption will
be significantly reduced from that of Mode 1 operation.
SHOULD END 400ns
READ OPERATION
FALLING EDGE OF
SHOULD END 400ns
FALLING EDGE OF
READ OPERATION
PRIOR TO NEXT
PRIOR TO NEXT
CONVST
CONVST
400ns MIN
400ns MIN
REGISTER
IS RESET
OUTPUT
SERIAL
REGISTER
SHIFT
IS RESET
OUTPUT
SERIAL
SHIFT
t
1
WAKE-UP
= 40ns MIN
t
1
TIME
= 6 s
REV. C