AD7724ASTZ-REEL Analog Devices Inc, AD7724ASTZ-REEL Datasheet
AD7724ASTZ-REEL
Specifications of AD7724ASTZ-REEL
Available stocks
Related parts for AD7724ASTZ-REEL
AD7724ASTZ-REEL Summary of contents
Page 1
GENERAL DESCRIPTION This device consists of two seventh order sigma-delta modula- tors. Each modulator converts its analog input signal into a high speed 1-bit data stream. The part operates from power supply and accepts a differential ...
Page 2
AD7724–SPECIFICATIONS MHz ac-coupled sine wave, REF2A = REF2B = 2 MCLK Parameter STATIC PERFORMANCE Integral Nonlinearity Offset Error 2 Gain Error Offset Error Drift Gain Error Drift Unipolar Mode Bipolar Mode ANALOG INPUTS Signal Input ...
Page 3
Parameter LOGIC OUTPUTS V , Output High Voltage Output Low Voltage OL POWER SUPPLIES AVDD/DVDD DVDD1 I (Total for AVDD, DVDD) DD Active Mode Standby Mode NOTES 1 Operating temperature range is as follows: A Version: –40°C ...
Page 4
AD7724 TIMING CHARACTERISTICS Limit at T MIN Parameter (A Version) f 100 MCLK DELAY 0.45 × MCLK 0.45 × MCLK ...
Page 5
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted) A DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0 ...
Page 6
AD7724 Mnemonic Description Analog Positive Supply Voltage ± 5%. AVDD AGND Ground reference point for analog circuitry. AVIN(–), AVIN(+) Analog Input to Modulator A. In unipolar operation, the analog input range on AVIN(+) is AVIN(–) to (AVIN(–) + ...
Page 7
TERMINOLOGY (IDEAL FIR FILTER USED WITH AD7724 [FIGURE 1]) Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale ...
Page 8
AD7724 –Typical Performance Characteristics (AVDD = DVDD = 5 CLKIN = 13 MHz ac-coupled sine wave, AIN = 20 kHz, Bipolar Mode unless otherwise noted) 110 100 90 SFDR 80 S/ (N+D) 70 ...
Page 9
FREQUENCY – MHz 0 CLKIN = 13MHz –20 SNR = 90.1dB –40 S/(N+D) = 89.2dB SFDR = –99.5dB –60 THD = –96.6dB 2ND = –100.9dB ...
Page 10
AD7724 CIRCUIT DESCRIPTION The AD7724 employs a sigma-delta conversion technique to convert the analog input into a digital pulse train. The analog input is continuously sampled by a switched capacitor modulator at twice the rate of the clock input frequency ...
Page 11
An alternative circuit configuration for driving the differential inputs to the AD7724 is shown in Figure 2.7nF 100 C 2.7nF R 100 C 2.7nF A capacitor between the two input pins sources or sinks charge to allow ...
Page 12
AD7724 Input Circuits Figures 12 and 13 show two simple circuits for bipolar mode operation. Both circuits accept a single-ended bipolar signal source and create the necessary differential signals at the input to the ADC. The circuit in Figure 12 ...
Page 13
The sampling clock generator should be referenced to the ana- log ground plane in a split ground system. However, this is not always possible because of system constraints. In many cases, the sampling clock must be derived from a higher ...
Page 14
AD7724 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead Plastic Thin Quad Flatpack (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC SQ 0.030 (0.75 0.018 (0.45 SEATING PLANE TOP VIEW (PINS DOWN) 0.006 (0.15 ...
Page 15
Revision History Location Data Sheet changed from REV REV. B. Additions to TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 16
...