AD7720BRUZ Analog Devices Inc, AD7720BRUZ Datasheet - Page 4
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AD7720BRUZ
Manufacturer Part Number
AD7720BRUZ
Description
SIGMA DELTA MODULATOR I.C.
Manufacturer
Analog Devices Inc
Datasheet
1.AD7720BRUZ-REEL.pdf
(16 pages)
Specifications of AD7720BRUZ
Number Of Bits
16
Sampling Rate (per Second)
12.5M
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
215mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-TSSOP (0.173", 4.40mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7720BRUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD7720
TIMING CHARACTERISTICS
Parameter
f
t
t
t
t
t
t
t
NOTE
Guaranteed by design.
MCLK
1
2
3
4
5
6
7
SCLK (O)
DATA (O)
RESET (I)
MCLK (I)
DVAL (O)
NOTE:
O SIGNIFIES AN OUTPUT
Limit at T
100
15
67
0.45
0.45
15
10
10
20
(B Version)
t
MCLK
NOTE:
I SIGNIFIES AN INPUT
O SIGNIFIES AN OUTPUT
t
t
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
MCLK
MCLK
MIN
, T
t
(AVDD = +5 V
1
MAX
t
5
t
3
OUTPUT
t
Figure 4. RESET Timing
6
PIN
TO
Figure 3. Data Timing
t
5%; DVDD = +5 V
4
t
50pF
2
C
L
Units
kHz min
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns max
–4–
I
200 A
I
1.6mA
OH
OL
t
7
5%; AGND = DGND = 0 V, REF2 = +2.5 V unless otherwise noted)
+1.6V
Master Clock Frequency
Conditions/Comments
12.5 MHz for Specified Performance
Master Clock Period
Master Clock Input High Time
Master Clock Input Low Time
Data Hold Time After SCLK Rising Edge
RESET Pulsewidth
RESET Low Time Before MCLK Rising
DVAL High Delay after RESET Low
REV. 0