AD7710AR-REEL Analog Devices Inc, AD7710AR-REEL Datasheet - Page 23

• Manufacturer Part Number: AD7710AR-REEL
• Description: IC,A/D CONVERTER,SINGLE,24-BIT,CMOS,SOP,24PIN
• Manufacturer: Analog Devices Inc

Specifications of AD7710AR-REEL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 24
• Sampling Rate (per Second): 1.03k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)

REV. G
Write Operation
Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the DRDY line and does not have any effect on the status of
DRDY. A write operation to the control register or the calibra-
tion register must always write 24 bits.
Figure 13a shows a write operation to the AD7710 with TFS
remaining low for the duration of the operation. A0 determines
whether a write operation transfers data to the control register
or to the calibration registers. This A0 signal must remain valid
for the duration of the serial write operation. As before, the
serial clock line should be low between read and write opera-
tions. The serial data to be loaded to the AD7710 must be valid
on the high level of the externally applied SCLK signal. Data is
clocked into the AD7710 on the high level of this SCLK signal
SDATA (I)
SDATA (I)
SCLK (I)
SCLK (I)
Figure 13a. External Clocking Mode, Control/Calibration Register Write Operation
TFS (I)
TFS (I)
A0 (I)
A0 (I)
Figure 13b. External Clocking Mode, Control/Calibration Register Write Operation
( TFS Returns High during Write Operation)
t
32
t
32
MSB
MSB
t
26
t
35
t
35
t
36
–23–
t
26
t
27
t
with the MSB transferred first. On the last active high time of
SCLK, the LSB is loaded to the AD7710.
Figure 13b shows a timing diagram for a write operation to the
AD7710 with TFS returning high during the operation and
returning low again to write the rest of the data-word. Timing
parameters and functions are very similar to those outlined for
Figure 13a, but Figure 13b has a number of additional times to
show timing relationships when TFS returns high in the middle
of transferring a word.
Data to be loaded to the AD7710 must be valid prior to the
rising edge of the SCLK signal. TFS should return high during
the low time of SCLK. After TFS returns low again, the next bit
of the data-word to be loaded to the AD7710 is clocked in on
next high level of the SCLK input. On the last active high time
of the SCLK input, the LSB is loaded to the AD7710.
27
BIT N
t
36
t
30
t
35
BIT N+1
LSB
t
34
t
36
t
33
AD7710